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公开(公告)号：US06735734B1
公开(公告)日：2004-05-11
申请号：US09561222
申请日：2000-04-28
IPC分类号： H04J322
CPC分类号： H04L1/0059 , H04L1/0041 , H04L1/0045 , H04L1/0065 , H04L1/0071 , H04L1/0083 , H04L2001/0093 , H04L2001/0098
摘要： A TDM data distribution system (10) includes a hub unit (12) with a multipoint transmitter (24) and any number of subscriber units (14), each of which has a multipoint receiver (28). A forward communication link (16) transmitted by the hub unit (12) exhibits a substantially constant baud and carrier frequency over a number of diverse modulation format (MF) time slots (42). However, the different MF slots (42) convey data using different modulation formats. Modulation order and coding rate may vary for different modulation formats. The multipoint transmitter (24) includes a number of encoding FEC processors (48), wherein each encoding FEC processor (48) is active only for selected ones of the different MF slots (42). When inactive, the internal states of the encoding FEC processors (48) are frozen. Each multipoint receiver (28) includes a decoding FEC processor (108) which is active only for MF slots (42) assigned to the same modulation format for which the decoding FEC processors (108) are programmed. When inactive, the internal states of the decoding FEC processors (108) are frozen.
摘要翻译： TDM数据分发系统（10）包括具有多点发射机（24）和任意数目的用户单元（14）的集线器单元（12），每个用户单元（14）具有多点接收机（28）。 由集线器单元（12）发送的前向通信链路（16）在多个不同调制格式（MF）时隙（42）上呈现基本恒定的波特率和载波频率。 然而，不同的MF时隙（42）使用不同的调制格式传送数据。 对于不同的调制格式，调制顺序和编码率可能会有所不同。 多点发射机（24）包括多个编码FEC处理器（48），其中每个编码FEC处理器（48）仅对不同MF时隙（42）中的选定的一个处理器有效。 当不活动时，编码FEC处理器（48）的内部状态被冻结。 每个多点接收器（28）包括解码FEC处理器（108），其仅对分配给解码FEC处理器（108）编程的相同调制格式的MF时隙（42）有效。 当不活动时，解码FEC处理器（108）的内部状态被冻结。
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公开(公告)号：US6141389A
公开(公告)日：2000-10-31
申请号：US350485
申请日：1999-07-09
CPC分类号： H04L27/2092
摘要： A digital communications modulator (10) includes a low speed IC (12) which performs encoding, symbol generation, pulse shaping, interpolation, linearization, and small amounts of frequency tuning. A complex, baseband digital communications signal (34) is output from the low speed IC (12) as a plurality of parallel streams of digital words. In a digital tuner 14 which includes a high speed IC (20), these parallel streams are digitally combined and digitally up-converted to an IF digital data stream (68) that may have a center frequency many times the baud rate. The high speed IC (20) also converts the digital stream to a broadband analog signal (40). The broadband analog signal (40) is processed through an analog band pass filter (42) that removes spectral images, reduces quantization errors, and limits the bandwidth approximately to the baud rate.
摘要翻译： 数字通信调制器（10）包括执行编码，符号产生，脉冲整形，插值，线性化和少量频率调谐的低速IC（12）。 从低速IC（12）输出复数的基带数字通信信号（34）作为数字字的多个平行流。 在包括高速IC（20）的数字调谐器14中，这些并行数据流被数字地组合并数字上变频成可以具有多倍于波特率的中心频率的IF数字数据流（68）。 高速IC（20）还将数字流转换为宽带模拟信号（40）。 宽带模拟信号（40）通过模拟带通滤波器（42）进行处理，该滤波器去除频谱图像，减少量化误差，并将带宽限制在波特率附近。
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公开(公告)号：US6005897A
公开(公告)日：1999-12-21
申请号：US991385
申请日：1997-12-16
CPC分类号： H04L1/006 , H03M13/253 , H03M13/256 , H03M13/2936 , H03M13/3776 , H03M13/3961 , H03M13/41 , H03M13/6325 , H03M13/6362 , H03M13/6508 , H04L1/0054 , H04L1/0065 , H04L1/0068 , H04L27/3416 , H04L27/3827 , H04L2027/003 , H04L2027/0055
摘要： A digital communication system (20) communicates using a polar amplitude phase shift keyed (P-APSK) phase point constellation (70, 70'). Pragmatic encoding and puncturing is accommodated. The pragmatic encoding uses the P-APSK constellation (70, 70') to simultaneously communicate both encoded and uncoded information bits. The P-APSK constellation (70, 70') has an even number of phase point rings (74, 76) and equal numbers of phase points (72) in pairs of the rings (74, 76). Encoded bits specify secondary modulation and uncoded bits specify primary modulation. The constellation (70, 70') is configured so that secondary modulation sub-constellations (78) include four phase points (72) arranged so that two of the four phase points (72) exhibit two phase angles at one magnitude and the other two of the four phase points exhibit phase angles that are at another magnitude. The difference between the phase angles at different magnitudes within a secondary sub-constellation (78) is constant.
摘要翻译： 数字通信系统（20）使用极振幅相移键控（P-APSK）相位点星座（70,70'）进行通信。 适应实用的编码和穿刺。 实际编码使用P-APSK星座（70,70'）来同时传送编码和未编码的信息比特。 P-APSK星座（70,70'）在成对的环（74,76）中具有偶数个相位点环（74,76）和相等数量的相位点（72）。 编码位指定二次调制，未编码位指定一次调制。 星座（70,70'）被配置为使得二次调制子星座（78）包括四个相位点（72），四个相位点（72）布置成使得四个相位点（72）中的两个在一个幅度上呈现两个相位角，另外两个相位点 四个相位点的相位角呈现出另一个幅度。 次级星座（78）内不同幅度的相位角之间的差异是恒定的。
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24.发明授权Rotationally invariant pragmatic trellis coded digital communication system and method therefor 失效旋转不变实用网格编码数字通信系统及其方法
公开(公告)号：US5995551A
公开(公告)日：1999-11-30
申请号：US912225
申请日：1997-08-15
CPC分类号： H04L27/186
摘要： A communication system (10) includes a rotationally invariant pragmatic trellis coded modulator (18) and demodulator (34). The modulator (18) partitions information bits (20) into primary (42) and secondary (44) data streams. The secondary data stream (44) is convolutionally encoded (70) then fed to the LSB of a phase mapper (76). The phase mapper (76) is arranged so that all pairs of adjacent phase data are generated from pairs of opposing polarity LSB inputs. The primary data stream (42) is differentially encoded through a dual channel differential encoder (50). The demodulator (34) convolutionally decodes (90) the secondary stream, then re-encodes (96) secondary stream estimates. The re-encoded secondary stream estimates are used to remove (102) the secondary modulation from phase value estimates. Adjusted phase value estimates are phase demodulated (104) and differentially decoded using a dual channel differential decoder (106).
摘要翻译： 通信系统（10）包括旋转不变的实际网格编码调制器（18）和解调器（34）。 调制器（18）将信息比特（20）分割成主（42）和次（44）数据流。 副数据流（44）被卷积编码（70），然后馈送到相位映射器（76）的LSB。 相位映射器（76）被布置成使得所有相邻的相位数据对都是由成对的极性LSB输入产生的。 主数据流（42）通过双通道差分编码器（50）进行差分编码。 解调器（34）对二次流进行卷积解码（90），然后重新编码（96）二次流估计。 重新编码的二次流估计用于从相位值估计中去除（102）二次调制。 调整后的相位值估计被相位解调（104），并使用双通道差分解码器（106）进行差分解码。
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公开(公告)号：US5764102A
公开(公告)日：1998-06-09
申请号：US800256
申请日：1997-02-13
CPC分类号： H04L7/0083 , H04L7/0062 , H04L7/10
摘要： A digital communication receiver (#10) takes one complex sample (#20) of a baseband analog signal (#12) per symbol. A rectangular to polar converter (#44) separates phase attributes of the complex samples from magnitude attributes during coarse symbol synchronization (#28). A phase processor (#48) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (#46) influences symbol timing only during clock adjustment opportunities. The magnitude processor (#46) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities during coarse symbol synchronization (#28). A fine symbol synchronizer (#42) is used to refine coarse estimates of symbol synchronization in a data-directed manner (#82) by estimating incoming signal at sub-symbol intervals before and sampling instants to control oscillator (#22) in response to incoming signal estimates.
摘要翻译： 数字通信接收机（＃10）每个符号采用基带模拟信号（＃12）的一个复样本（＃20）。 矩形到极化转换器（＃44）在粗符号同步期间将复数样本的相位属性与幅度属性分开（＃28）。 相位处理器（＃48）识别当连续符号之间出现相对大的相位变化时发生的时钟调整机会。 幅度处理器（＃46）仅在时钟调整机会期间影响符号定时。 幅度处理器（＃46）在时钟调整机会期间检测到减小的幅度变化时，在锁相环中提前符号定时，并且在粗略符号同步期间在时钟调整机会期间检测到增加幅度变化时延迟符号定时（＃28）。 使用精细符号同步器（＃42），以数据方式（＃82）来细化粗略估计符号同步（＃82），通过在子符号间隔之前估计输入信号，并响应于 传入信号估计。
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公开(公告)号：US5553098A
公开(公告)日：1996-09-03
申请号：US226669
申请日：1994-04-12
IPC分类号： H04L27/00 , H04L27/233 , H04L27/14
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0055
摘要： A selectable demodulator (32) operates in the phase domain to implement a coherent demodulation path (40) and a differentially coherent demodulation path (42). The coherent path (40) includes a differential encoder circuit (46) to produce coherently demodulated differential data. Magnitude converters (62, 62') convert phase errors in each path into magnitude values. A comparison circuit (66) compares magnitude values from the two paths (40, 42) and selects the path encountering the least phase error. A selection circuit (60) provides data codes demodulated in accordance with the selection.
摘要翻译： 可选择的解调器（32）在相位域中操作以实现相干解调路径（40）和差分相干解调路径（42）。 相干路径（40）包括用于产生相干解调的差分数据的差分编码器电路（46）。 幅度转换器（62,62'）将每个路径中的相位误差转换为幅度值。 比较电路（66）比较来自两个路径（40,42）的幅度值，并选择遇到最小相位误差的路径。 选择电路（60）提供根据选择解调的数据代码。
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27.发明授权Multi-rate branch metric processor for maximum-likelihood convolutional decoder 失效用于最大似然卷积解码器的多速率分支度量处理器
公开(公告)号：US4500994A
公开(公告)日：1985-02-19
申请号：US432489
申请日：1982-10-04
CPC分类号： H03M13/41
摘要： A branch metric processor for use in a maximum-likelihood convolutional decoder accepts a set of soft-decision symbols, an indicator of a level of quantization thereof and a set of erase control signals and generates branch metrics for base code rates of 1/3 and 1/2. The apparatus represents a substantial reduction in complexity over prior art devices. Erasure of selected symbols allows the processor to generate branch metrics for higher code rates and is advantageous in very low code rate applications.
摘要翻译： 用于最大似然卷积解码器的分支度量处理器接受一组软判决符号，其量化级别的指示符和一组擦除控制信号，并产生用于基本码率为1/3的分支度量， 1/2。 该装置代表了现有技术装置的复杂性的显着降低。 擦除所选择的符号允许处理器产生用于更高码率的分支度量，并且在非常低的码率应用中是有利的。
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公开(公告)号：USRE43963E1
公开(公告)日：2013-02-05
申请号：US12814529
申请日：2010-06-14
CPC分类号： H04L25/03834 , H04B1/717 , H04B1/719 , H04B2201/70706 , H04L27/2614 , H04L27/2627 , H04L27/3411 , H04L27/3494 , H04L27/363
摘要： A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies the constrained-envelope signal stream (112) and transmits it as a radio-frequency broadcast signal (26).
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公开(公告)号：US07783260B2
公开(公告)日：2010-08-24
申请号：US11417477
申请日：2006-04-27
IPC分类号： H04B17/00
CPC分类号： H03G3/3047 , H03F1/0205 , H03F3/24 , H03F2200/165 , H03F2200/258 , H03G3/3042 , H04B1/0475 , H04L27/2624
摘要： A signal processing system according to various aspects of the present invention includes an excursion signal generator, a scaling system and a filter system. The excursion signal generator identifies a peak portion of a signal that exceeds a threshold and generates a corresponding excursion signal. The scaling system applies a real scale factor to contiguous sets of excursion samples in order to optimize peak-reduction performance. The filter system filters the excursion signal to remove unwanted frequency components from the excursion signal. The filtered excursion signal may then be subtracted from a delayed version of the original signal to reduce the peak. The signal processing system may also control power consumption by adjusting the threshold. The signal processing system may additionally adjust the scale of the excursion signal and/or individual channel signals, such as to meet constraints on channel noise and output spectrum, or to optimize peak reduction. The magnitude threshold, excursion signal and/or individual channel signals may also be adaptively adjusted based on, for example, a channel signal quality such as a noise level specification.
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公开(公告)号：US07747224B2
公开(公告)日：2010-06-29
申请号：US12335969
申请日：2008-12-16
IPC分类号： H04B17/00
CPC分类号： H03G3/3047 , H03F1/0205 , H03F3/24 , H03F2200/165 , H03F2200/258 , H03G3/3042 , H04B1/0475 , H04L27/2624
摘要： A signal processing system according to various aspects of the present invention includes an excursion signal generator, a scaling system and a filter system. The excursion signal generator identifies a peak portion of a signal that exceeds a threshold and generates a corresponding excursion signal. The scaling system applies a real scale factor to contiguous sets of excursion samples in order to optimize peak-reduction performance. The filter system filters the excursion signal to remove unwanted frequency components from the excursion signal. The filtered excursion signal may then be subtracted from a delayed version of the original signal to reduce the peak. The signal processing system may also control power consumption by adjusting the threshold. The signal processing system may additionally adjust the scale of the excursion signal and/or individual channel signals, such as to meet constraints on channel noise and output spectrum, or to optimize peak reduction. The magnitude threshold, excursion signal and/or individual channel signals may also be adaptively adjusted based on, for example, a channel signal quality such as a noise level specification.
摘要翻译： 根据本发明的各个方面的信号处理系统包括偏移信号发生器，缩放系统和滤波器系统。 偏移信号发生器识别超过阈值的信号的峰值部分，并产生相应的偏移信号。 缩放系统将实际比例因子应用于连续的偏移样本集，以优化峰值降低性能。 滤波器系统对偏移信号进行滤波以从偏移信号中去除不需要的频率分量。 然后可以从原始信号的延迟版本中减去滤波的偏移信号以减小峰值。 信号处理系统还可以通过调整阈值来控制功耗。 信号处理系统可以另外调整偏移信号和/或单个信道信号的比例，例如以满足对信道噪声和输出频谱的约束，或者优化峰值减小。 幅度阈值，偏移信号和/或单个信道信号也可以基于例如诸如噪声电平指定的信道信号质量自适应地调整。
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