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公开(公告)号：US20210367456A1
公开(公告)日：2021-11-25
申请号：US16878782
申请日：2020-05-20
Inventor： Michal Toula
Abstract: A wireless charging receiver includes a controller configured to determine that a first overvoltage threshold is met and based thereon enable a first switch to couple an output of a rectifier to electrical ground through a first resistor, to determine that a second overvoltage threshold is met and based thereon enable receive resonant circuit switches to short circuit a receive resonant circuit, to determine that a hysteresis threshold is met and based thereon disable the receive resonant circuit switches to open circuit the receive resonant circuit, and to determine that a hysteresis cycle threshold is met and that the receive resonant circuit switches are disabled and based thereon enable the second switch to couple the second resistor to the electrical ground and to communicate to wireless charging transmitter to decrease the power level on wireless charging receiver side.
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公开(公告)号：US20210357344A1
公开(公告)日：2021-11-18
申请号：US17245894
申请日：2021-04-30
Inventor： Fred Rennig , Vaclav Dvorak , Ludek Beran
IPC: G06F13/362 , H04L12/40 , G06F11/07
Abstract: An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.
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公开(公告)号：US20210328563A1
公开(公告)日：2021-10-21
申请号：US17362276
申请日：2021-06-29
Inventor： Sandor PETENYI
Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.
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公开(公告)号：US20210303504A1
公开(公告)日：2021-09-30
申请号：US17199418
申请日：2021-03-11
Inventor： Rolf Nandlinger , Radek Olexa
Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.
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公开(公告)号：US10788848B2
公开(公告)日：2020-09-29
申请号：US16285330
申请日：2019-02-26
Inventor： Sandor Petenyi
Abstract: An amplifier stage of an LDO regulator circuit includes an amplifier stage that generates a drive signal in response to a first voltage difference an output voltage of the LDO regulator circuit and a reference voltage. A drive stage having a quiescent current consumption is configured to generate a control signal in response to the drive signal. The control signal is applied to the control terminal of a power transistor. A dropout detector senses whether the LDO regulator circuit is operating in closed loop regulation mode or in open loop dropout mode by sensing a second difference in voltage between the drive signal and the control signal. A quiescent current limiter circuit responds to the sensed second difference by controlling the quiescent current consumption of the drive stage, and in particular limiting current consumption when the LDO regulator circuit is operating in the open loop dropout mode.
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Patent Agency Ranking
公开(公告)号：US10720840B2
公开(公告)日：2020-07-21
申请号：US16222557
申请日：2018-12-17
Inventor： Matthieu Thomas , Michele Suraci , Massimo Mazzucco
Abstract: A DC-DC converter circuit including at least: a first step down converter having a first pair of switching devices in a half bridge configuration. A second step down converter includes a second pair of switching devices in a half bridge configuration. The first and second step down converters are connected in parallel to an output node connected to an output coil and receive command signals. A feedback loop includes a synchronization module receiving the gate control signals of high side switching devices and adjusts as a function of the gate control signals a delay in a signal path from the command signal to each gate control signal of the high side switching device to synchronize the gate control signals.
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公开(公告)号：US20190294572A1
公开(公告)日：2019-09-26
申请号：US16360229
申请日：2019-03-21
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US20180342594A1
公开(公告)日：2018-11-29
申请号：US15606778
申请日：2017-05-26
Inventor： Patrik Vacula , Milos Vacula , Vlastimil Kote , Adam Kubacak , Milan Lzicar
IPC: H01L29/423 , H01L27/088 , H01L29/06 , H01L29/40 , H01L29/66 , H01L29/778
Abstract: The present disclosure is directed to a plurality of waffle gate parallel transistors having a shared gate on a surface of a semiconductor substrate. The shared gate has connected channels that form a plurality of squares, lines of each of the squares over the perimeter of a respective source or drain region of the plurality of waffle gate parallel transistors. The shared gate includes squares of a first size and shape and a second size and shape. The squares having the first size and shape are each over a respective source region and the squares having the second size and shape are each over a respective drain region. Each of the squares having a first size and shape share at least one side with one of the squares having the second size and shape.
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29.发明申请公开(公告)号：US20180063638A1
公开(公告)日：2018-03-01
申请号：US15473812
申请日：2017-03-30
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics Design and Application S.R.O. , STMicroelectronics (Alps) SAS
Inventor： Jean Claude Bini , Dragos Davidescu , Igor Cesko , Jonathan Cottinet
CPC classification number: H04R3/005 , G10K11/346 , H04R1/406 , H04R3/04 , H04R19/005 , H04R2201/003 , H04R2430/23
Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.
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公开(公告)号：US20170102724A1
公开(公告)日：2017-04-13
申请号：US14881498
申请日：2015-10-13
Inventor： Sandor PETENYI
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: A voltage regulator includes an input terminal to receive an input voltage, an output terminal to supply an output voltage, a power transistor, a differential amplifier, a driver, a dropout detector and a bias current limiter. The differential amplifier provides a drive signal based on a difference between a voltage reference and a feedback signal corresponding to the output voltage. The driver includes an impedance device, and a driver transistor that receives the drive signal so as to vary a bias current to a control terminal of the power transistor. The dropout detector and the bias current limiter is coupled to the input terminal, the impedance device, and the output terminal and includes first and second transistors coupled together, and a bias current generator coupled to the second transistor.
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