公开(公告)号：US06670249B1

公开(公告)日：2003-12-30

申请号：US09686879

申请日：2000-10-12

Applicant: Hong-Tsz Pan ,  Tung-Po Chen

Inventor： Hong-Tsz Pan ,  Tung-Po Chen

IPC: H01L21336

CPC classification number: H01L21/28518

Abstract: A process for forming high temperature stable self-aligned suicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal suicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal suicide layer profile can be ensured even if subsequent high temperature processing operations are performed.

Abstract translation: 用于形成高温稳定的自对准硅化物层的方法，不仅在硅化反应中使用高温而不仅能够均匀且均匀地形成，而且还可以经受其它后续的高温热处理操作并保持稳定的金属硅化物层 之后的档案。 而且，通过适当地调节非晶注入参数，可以获得所需的金属硅化物层的厚度和均匀性，而使用氮化钛盖层有助于在高温形成期间稳定金属硅化物层，并且稳定且均匀的金属硅化物 即使执行后续的高温处理操作，也可以确保层的轮廓。

公开(公告)号：US06350646B1

公开(公告)日：2002-02-26

申请号：US09484786

申请日：2000-01-18

Applicant: Tung-Po Chen ,  Yung-Chang Lin

Inventor： Tung-Po Chen ,  Yung-Chang Lin

IPC: H01L218242

CPC classification number: H01L21/76831 ,  H01L21/76802 ,  H01L27/10855 ,  H01L27/10894

Abstract: A method for manufacturing a semiconductor device is disclosed. The method can reduce thermal budget in node contact application. It includes mainly the following processes. A substrate is first provided, then a dielectric layer is formed over the substrate. Next, a node contact opening through the dielectric layer to top surface of the substrate is formed by coating the dielectric layer with a photoresist layer, patterning the photoresist layer with pattern of a node contact by exposure and development, then etching the dielectric layer until top surface of said substrate exposed using said patterned photoresist layer as a mask. Subsequently, the photoresist layer is removed. Finally, a silicon nitride layer is formed on inside wall of the node contact opening by rapid thermal chemical vapor deposition (RTCVD).

Abstract translation: 公开了一种制造半导体器件的方法。 该方法可以降低节点接触应用中的热预算。 它主要包括以下过程。 首先提供衬底，然后在衬底上形成电介质层。 接下来，通过介电层到基板的顶表面的节点接触开口通过用光致抗蚀剂层涂覆介电层而形成，通过曝光和显影对具有节点接触图案的光致抗蚀剂层进行图案化，然后蚀刻介电层直到顶部 使用所述图案化的光致抗蚀剂层作为掩模曝光所述衬底的表面。 随后，去除光致抗蚀剂层。 最后，通过快速热化学气相沉积（RTCVD）在节点接触开口的内壁上形成氮化硅层。

公开(公告)号：US06297112B1

公开(公告)日：2001-10-02

申请号：US09497668

申请日：2000-02-04

Applicant: Tony Lin ,  Tung-Po Chen ,  Ming-Yin Hao

Inventor： Tony Lin ,  Tung-Po Chen ,  Ming-Yin Hao

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/266 ,  H01L29/6656 ,  Y10S438/976

Abstract: The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor. The portion of the first ion implantation layer that is not covered by the second ion implantation layer is used as a lightly doped drain (LDD). The protection layer is used to protect the surface of the silicon substrate from being etched during the RCA cleaning process so as to prevent an increase of the electrical resistance of the LDD.

Abstract translation: 本发明提供一种在半导体晶片上形成PMOS晶体管或NMOS晶体管的方法。 半导体晶片包括硅衬底和位于硅衬底的预定区域上的栅极。 首先，在半导体晶片上形成由氮化硅制成的均匀厚度的保护层，以覆盖栅极的表面。 然后，进行第一离子注入工艺以在栅极周围的硅衬底上形成具有第一预定厚度的第一离子注入层。 然后，执行RCA清洁处理以去除半导体晶片上的杂质。 接下来，在栅极周围形成间隔物。 最后，执行第二离子注入工艺以在栅极周围的硅衬底上形成具有第二预定厚度的第二离子注入层。 第二离子注入层用作MOS晶体管的源极或漏极（S / D）。 未被第二离子注入层覆盖的第一离子注入层的部分用作轻掺杂漏极（LDD）。 保护层用于在RCA清洁过程中保护硅衬底的表面不被蚀刻，以防止LDD的电阻增加。

公开(公告)号：US06187644B1

公开(公告)日：2001-02-13

申请号：US09391934

申请日：1999-09-08

Applicant: Tony Lin ,  Tung-Po Chen

Inventor： Tony Lin ,  Tung-Po Chen

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/28123 ,  H01L29/66545 ,  Y10S438/952

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate, followed by forming a gate oxide layer and a conductive layer over the substrate. An anti-reflective coating is then formed on the conductive layer. After patterning to etch the anti-reflective coating and the conductive layer, a gate region is thus formed. A dielectric layer is formed over the gate region, and is then subjected to etching back, therefore forming an offset spacer on sidewall of the gate region while simultaneously removing surface oxide of the anti-reflective coating. Finally, anti-reflective coating is removed.

Abstract translation: 公开了一种用于形成半导体器件的方法。 该方法包括提供半导体衬底，随后在衬底上形成栅极氧化物层和导电层。 然后在导电层上形成抗反射涂层。 在图案化以蚀刻抗反射涂层和导电层之后，因此形成栅极区域。 在栅极区域上形成电介质层，然后对其进行蚀刻，从而在栅极区域的侧壁上形成偏移间隔物，同时去除抗反射涂层的表面氧化物。 最后，去除抗反射涂层。

公开(公告)号：US6150205A

公开(公告)日：2000-11-21

申请号：US227761

申请日：1999-01-08

Applicant: Tung-Po Chen ,  Yung-Chang Lin

Inventor： Tung-Po Chen ,  Yung-Chang Lin

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method of fabricating a dual gate. A first conductive type region and a second conductive type region isolated by an isolation structure is provided. A polysilicon layer is formed on the first and the second conductive type regions. A diffusion layer containing second type conductive ions is formed on a second part of the polysilicon layer which covers the second conductive type region. First conductive ions are implanted into a part of the first conductive region which covers the first conductive type region. A first thermal process is performed. A metal layer is formed, and a second thermal process is performed, so that the metal layer is transformed into a metal silicide layer. A dielectric layer is formed on the metal layer. The dielectric layer, the metal silicide layer, diffusion layer, and the polysilicon layer are patterned to form a dual gate.

Abstract translation: 一种制造双门的方法。 提供了由隔离结构隔离的第一导电类型区域和第二导电类型区域。 在第一和第二导电类型区域上形成多晶硅层。 在覆盖第二导电类型区域的多晶硅层的第二部分上形成包含第二类型导电离子的扩散层。 第一导电离子被注入到覆盖第一导电类型区域的第一导电区域的一部分中。 执行第一热处理。 形成金属层，进行第二热处理，使金属层转变为金属硅化物层。 在金属层上形成电介质层。 将电介质层，金属硅化物层，扩散层和多晶硅层图案化以形成双栅极。

公开(公告)号：US6124621A

公开(公告)日：2000-09-26

申请号：US314528

申请日：1999-05-19

Applicant: Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

Inventor： Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/6659 ,  H01L29/6656 ,  Y10S257/90 ,  Y10S257/915

Abstract: A structure of a spacer in a semiconductor device is disclosed. Firstly, a gate without a spacer is provided on a substrate. A first insulating layer is formed on the sidewall of the gate. After a lightly doped drain is subsequently achieved in the substrate, a second insulating layer is formed on the first spacer. The process following this embodiment described above is to form a heavily doped drain in the substrate, then the whole MOSFET fabrication is completed. The present invention can enhance the stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract translation: 公开了半导体器件中的间隔物的结构。 首先，在衬底上设置没有间隔物的栅极。 第一绝缘层形成在栅极的侧壁上。 在衬底中随后实现轻掺杂漏极之后，在第一间隔物上形成第二绝缘层。 按照上述实施例描述的工艺是在衬底中形成重掺杂漏极，然后完成整个MOSFET制造。 本发明可以提高门的电阻的稳定性并减少机器的污染。 因此，MOSFET的制造的质量和效率将得到提高。

公开(公告)号：US6060349A

公开(公告)日：2000-05-09

申请号：US152449

申请日：1998-09-14

Applicant: Tzu-Min Peng ,  Keh-Ching Huang ,  Tung-Po Chen ,  Tz-Guei Jung

Inventor： Tzu-Min Peng ,  Keh-Ching Huang ,  Tung-Po Chen ,  Tz-Guei Jung

IPC: H01L21/8242

CPC classification number: H01L27/10844 ,  H01L27/10852

Abstract: A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.

Abstract translation: 用于制造嵌入式动态随机存取存储器（DRAM）的平面化方法。 在半导体衬底上形成多个金属氧化物半导体（MOS）晶体管和多个电容器之后，在衬底上形成第一层间二电极（ILD）层。 嵌入式DRAM被分成存储区域和逻辑区域。 接下来，进行平坦化。 形成虚设的金属层并与逻辑区域中的MOS晶体管的可互换的源/漏区耦合。 然后在逻辑区域上形成第二ILD层以补偿逻辑区域和存储区域之间的高度差异。 然后，在逻辑区域中形成通孔/插头以延伸第一金属层。 在衬底上形成具有所需接触窗/插塞的第二金属层。

公开(公告)号：US6022795A

公开(公告)日：2000-02-08

申请号：US73861

申请日：1998-05-07

Applicant: Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

Inventor： Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/3205

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28518

Abstract: A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

公开(公告)号：US5893751A

公开(公告)日：1999-04-13

申请号：US736939

申请日：1996-10-25

Applicant: Jason Jenq ,  Tung-Po Chen

Inventor： Jason Jenq ,  Tung-Po Chen

IPC: H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518

Abstract: An improved self-aligned silicide manufacturing method in which prior to the formation of a heat resistant metallic layer on top of a silicon substrate, a treatment of exposed surfaces of a gate terminal and source/drain diffusion regions is performed to increase surface roughness enabling an increase in crystallization nucleus number, as well as lowering crystallization temperature.

Abstract translation: 一种改进的自对准硅化物制造方法，其中在硅衬底顶部形成耐热金属层之前，执行对栅极端子和源极/漏极扩散区域的暴露表面的处理，以增加表面粗糙度，从而能够 结晶核数增加，结晶温度降低。

公开(公告)号：US20090186459A1

公开(公告)日：2009-07-23

申请号：US12342031

申请日：2008-12-22

Applicant: Tung-Po Chen

Inventor： Tung-Po Chen

IPC: H01L21/336

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of manufacturing a non-volatile memory is provided. A substrate is provided and then a number of stacked gate structures are formed on the substrate. Each of the stacked gate structures includes a tunneling dielectric layer, a floating gate, a first inter-gate dielectric layer, a control gate and a cap layer. A source region is formed in the substrate, and a second inter-gate dielectric layer is formed over the substrate. A number of polysilicon select gates are formed on one side of the stacked gate structures. The select gates connect the stacked gate structures together to form a memory cell column. A spacer is formed on each sidewall of the memory cell column. A drain region is formed in the substrate on one side of the memory cell column. A silicidation process is carried out to convert the polysilicon constituting the select gate into a silicide material.

Abstract translation: 提供一种制造非易失性存储器的方法。 提供衬底，然后在衬底上形成多个堆叠的栅极结构。 堆叠的栅极结构中的每一个包括隧道电介质层，浮置栅极，第一栅极间介电层，控制栅极和盖层。 源极区域形成在衬底中，并且在衬底上形成第二栅极间电介质层。 多个多晶硅选择栅极形成在堆叠栅极结构的一侧。 选择栅极将堆叠的栅极结构连接在一起以形成存储单元列。 在存储单元列的每个侧壁上形成间隔物。 在存储单元列的一侧上的衬底中形成漏极区。 进行硅化处理以将构成选择栅极的多晶硅转换为硅化物材料。