公开(公告)号：US07169661B2

公开(公告)日：2007-01-30

申请号：US10823238

申请日：2004-04-12

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien

IPC: H01L21/8238

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L27/0802

Abstract: A process of forming a high resistance CMOS resistor with a relatively small die size is provided. According to an aspect of the present invention, the process of fabricating a high resistance resistor is a standard CMOS process that does not require any additional masking. An n-well is firstly formed in a p-type silicon substrate. A nitride film is then deposited and patterned to form a patterned mask layer. The patterned mask layer serves as a mask. A p-field region is formed in the n-well to form a CMOS resistor. The CMOS resistor according to the present invention has a resistance of 10 kΩ–20 kΩ per square.

Abstract translation: 提供了形成具有相对小的管芯尺寸的高电阻CMOS电阻器的工艺。 根据本发明的一个方面，制造高电阻电阻器的过程是不需要额外掩蔽的标准CMOS工艺。 首先在p型硅衬底中形成n阱。 然后沉积和图案化氮化物膜以形成图案化掩模层。 图案化掩模层用作掩模。 在n阱中形成p场区以形成CMOS电阻。 根据本发明的CMOS电阻器具有10kOmega-20kOmega每平方的电阻。

公开(公告)号：US20060197153A1

公开(公告)日：2006-09-07

申请号：US11065497

申请日：2005-02-23

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/7811 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095

Abstract: A structure of a vertical transistor with field region is provided. The vertical transistor comprises a field-doping region formed in a substrate next to a core region of the vertical transistor. By modulating the doping density, length, and geometrical pattern of the field region, and by connecting the field region to respective well of rim core regions of the vertical transistor, the present invention realizes a stable breakdown voltage with short length of the field region. Therefore, the device area and the manufacturing cost can be reduced.

Abstract translation: 提供具有场区域的垂直晶体管的结构。 垂直晶体管包括形成在垂直晶体管的芯区域旁边的衬底中的场掺杂区域。 通过调制场区域的掺杂密度，长度和几何图案，并且通过将场区域连接到垂直晶体管的边缘芯区域的相应阱，本发明实现了场区域的短长度的稳定的击穿电压。 因此，可以减少设备面积和制造成本。

公开(公告)号：US07042028B1

公开(公告)日：2006-05-09

申请号：US11079994

申请日：2005-03-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu G. Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu G. Lin ,  Ta-yung Yang

IPC: H01L23/60 ,  H01L29/66 ,  H02H9/00

CPC classification number: H01L27/0262

Abstract: An electrostatic discharge (ESD) device, which functions like a diode during normal IC operation and like a SCR during an electrostatic discharge event, is provided. To form an equivalent SCR structure, the ESD device includes a plurality of N+ regions and a plurality of P+ regions formed inside an N-well. The P+ regions and the N+ regions are formed adjacent to each other in a sequence, and the regions located at both ends of the sequence are the N+ regions. In addition, the ESD device is integrated with a pad and is formed under the pad. Furthermore, since the pad has a large surface area and is plated to be a good electrical conductor, the current distribution in the ESD device is uniform.

Abstract translation: 提供了在静电放电事件期间在正常IC操作期间像二极管一样工作的静电放电（ESD）装置。 为了形成等效的SCR结构，ESD器件包括形成在N阱内的多个N +区和多个P +区。 P +区域和N +区域以序列形式彼此相邻，并且位于序列两端的区域是N +区域。 此外，ESD装置与垫整合并形成在垫下。 此外，由于焊盘具有大的表面积并被电镀成良好的导体，所以ESD器件中的电流分布是均匀的。

公开(公告)号：US07923787B2

公开(公告)日：2011-04-12

申请号：US11913044

申请日：2005-10-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-Yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-Yung Yang

IPC: H01L21/70

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.

Abstract translation: 提供了具有隔离结构的MOSFET。 N型MOSFET包括设置在P型衬底中的第一N型掩埋层和P型外延层。 P型FET包括第二N型掩埋层和设置在P型衬底中的P型外延层。 第一N型掩埋层和P型外延层提供FET之间的隔离。 此外，设置在P型外延层中的多个分离的P型区域进一步提供隔离效果。 在第一厚电场氧化物层和第一P型区域之间存在用于提高N型FET的击穿电压的第一间隙。 在第二厚场氧化物层和第二N阱之间存在第二间隙，用于提高P型FET的击穿电压。

公开(公告)号：US20090050962A1

公开(公告)日：2009-02-26

申请号：US11913037

申请日：2005-10-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/0928 ,  H01L21/823878 ,  H01L21/823892

Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.

Abstract translation: 提供了具有用于单片集成的隔离结构的MOSFET器件。 P型MOSFET包括设置在P型衬底中的第一N阱，设置在第一N阱中的第一P型区，设置在第一P型区中的P +漏极区，第一源电极 形成有P +源极区域和N +接触区域。 第一个N阱围绕着P +源极区域和N +接触区域。 N型MOSFET包括设置在P型衬底中的第二N阱，设置在第二N阱中的第二P型区，设置在第二N阱中的N +漏极区，第二源电极 形成有N +源区和P +接触区。 第二P型区围绕N +源极区域和P +接触区域。 多个分离的P型区域设置在P型衬底中以提供晶体管的隔离。

公开(公告)号：US07285837B2

公开(公告)日：2007-10-23

申请号：US10905677

申请日：2005-01-17

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu G. Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu G. Lin ,  Ta-yung Yang

IPC: H01L23/58

CPC classification number: H01L27/0255

Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.

Abstract translation: 提供了与焊盘集成的静电放电（ESD）器件的结构。 ESD器件与焊盘集成并形成在焊盘下方。 通过使用垫下的区域，ESD器件不占用集成电路的额外空间。 此外，由于焊盘是大的，板状的和理想的导体，所以连接的焊盘和ESD器件能够平均地在ESD器件中分配电流。

公开(公告)号：US20070052030A1

公开(公告)日：2007-03-08

申请号：US11222707

申请日：2005-09-08

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L23/62

CPC classification number: H01L27/0262

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract translation: 提供具有寄生可控硅整流器（SCR）结构和可控保持电流的静电放电（ESD）器件。 在第一N +掺杂区域和第一P +掺杂区域之间保持第一距离，并且在第二P +掺杂区域和第三N +掺杂区域之间保持第二距离。 此外，通过调制第一距离和第二距离，可以将ESD装置的保持电流设定为特定值。 保持电流与第一距离和第二距离成反比。

公开(公告)号：US20060220170A1

公开(公告)日：2006-10-05

申请号：US11096959

申请日：2005-03-31

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

IPC: H01L29/00

CPC classification number: H01L21/823493 ,  H01L21/823418 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: A high-voltage MOSFET having isolation structure is provided. An N-type MOSFET includes a first deep N-type well. A first P-type region is formed in the first deep N-type well to enclose a first source region and a first contact region. A first drain region is formed in the first deep N-type well. A P-type MOSFET includes a second deep N-type well. A second P-type region is formed in the second deep N-type well to enclose a second drain region. A second source region and a second contact region are formed in the second deep N-type well. A polysilicon gate oxidation layer is disposed above the thin gate oxidation layer and the thick field oxidation layer to control the current in the channel of the MOSFET. Separated P-type regions provide further isolation between MOSFETs. A first gap and a second gap increase the breakdown voltage of the high-voltage MOSFET.

Abstract translation: 提供了具有隔离结构的高压MOSFET。 N型MOSFET包括第一深N型阱。 在第一深N型阱中形成第一P型区域以包围第一源极区域和第一接触区域。 在第一深N型阱中形成第一漏区。 P型MOSFET包括第二深N型阱。 在第二深N型阱中形成第二P型区域以包围第二漏极区域。 在第二深N型阱中形成第二源区和第二接触区。 多晶硅栅极氧化层设置在薄栅氧化层和厚场氧化层之上，以控制MOSFET沟道中的电流。 分离的P型区域提供MOSFET之间的进一步隔离。 第一间隙和第二间隙增加了高压MOSFET的击穿电压。

公开(公告)号：US07102194B2

公开(公告)日：2006-09-05

申请号：US10919916

申请日：2004-08-16

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu G. Lin ,  Tuo-Hsin Chien

IPC: H01L29/94

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/42368

Abstract: A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.

Abstract translation: 根据本发明的高电压LDMOS晶体管包括N阱扩展漏极区中的至少一个P场模块。 P场块在N阱中形成结场，用于均衡漏极区和源极区之间的寄生电容的电容，并在击穿之前完全耗尽漂移区。 因此实现更高的击穿电压，因此允许具有较高掺杂密度的N阱。 源极区域和P场区域封装漏极区域，这使得LDMOS晶体管自隔离。

公开(公告)号：US20060157790A1

公开(公告)日：2006-07-20

申请号：US10905677

申请日：2005-01-17

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu G. Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu G. Lin ,  Ta-yung Yang

IPC: H01L23/62

CPC classification number: H01L27/0255

Abstract: A structure of an electrostatic discharge (ESD) device integrated with a pad is provided. The ESD device is integrated with the pad and formed under the pad. By using the area under the pad, the ESD device does not occupy additional space of an integrated circuit. Furthermore, since the pad is a large, plate, and ideal conductor, the connected pad and the ESD device are capable of distributing current in the ESD device averagely.

Abstract translation: 提供了与焊盘集成的静电放电（ESD）器件的结构。 ESD器件与焊盘集成并形成在焊盘下方。 通过使用垫下的区域，ESD器件不占用集成电路的额外空间。 此外，由于焊盘是大的，板状的和理想的导体，所以连接的焊盘和ESD器件能够平均地在ESD器件中分配电流。