公开(公告)号：US20250089349A1

公开(公告)日：2025-03-13

申请号：US18381639

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin

IPC: H01L27/06 ,  H01L21/265 ,  H01L21/762 ,  H01L29/78

Abstract: A structure with a capacitor and a fin transistor includes a substrate. The substrate includes a capacitor region and a fin transistor region. A mesa is disposed within the capacitor region of the substrate. The mesa protrudes from a surface of the substrate. The mesa includes a top surface and two sloping surfaces. Each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate. A doping region is disposed within the mesa. A capacitor electrode is only disposed on the top surface. A capacitor dielectric layer is disposed between the capacitor electrode and the doping region.

公开(公告)号：US20250089281A1

公开(公告)日：2025-03-13

申请号：US18487110

申请日：2023-10-15

Applicant: United Microelectronics Corp.

Inventor： Wen-Kai Lin ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L29/872 ,  H01L29/40 ,  H01L29/47 ,  H01L29/66

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate including a fin portion, first and second doped regions having a first conductive type, first and second contacts, and first and second metal silicide layers. The fin portion protrudes from a surface of the substrate. The first doped region is disposed in the fin portion. The second doped region is disposed in the fin portion and connected to the first doped region. A doping concentration of the second doped region is greater than that of the first doped region. The first contact is disposed on the first doped region. The second contact is disposed on the second doped region. The first metal silicide layer is disposed between the first contact and the first doped region. The second metal silicide layer is disposed between the second contact and the second doped region.

公开(公告)号：US20250072042A1

公开(公告)日：2025-02-27

申请号：US18376450

申请日：2023-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Hsin Chen ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-cheng Su

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

公开(公告)号：US20250063803A1

公开(公告)日：2025-02-20

申请号：US18368552

申请日：2023-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Kun-Szu Tseng ,  Sheng-Yuan Hsueh ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L27/06

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, performing a monolayer doping (MLD) process on the first fin-shaped structure, and then performing an anneal process for driving dopants into the first fin-shaped structure. Preferably, the MLD process is further accomplished by first performing a wet chemical doping process on the first fin-shaped structure and then forming a cap layer on the non-MOSCAP region and the MOSCAP region.

公开(公告)号：US20250056818A1

公开(公告)日：2025-02-13

申请号：US18367467

申请日：2023-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a bottom portion, a middle portion, a top portion, and a base portion between the bottom portion and the substrate. Preferably, the bottom portion is surrounded by a shallow trench isolation (STI), a gate oxide layer is disposed on the fin-shaped structure and the STI, a bottom surface of the gate oxide layer is higher than a top surface of the base portion, a width of a top surface of the bottom portion is greater than half the width of the bottom surface of the bottom portion, and a tip of the top portion includes a tapered portion.

公开(公告)号：US12224001B2

公开(公告)日：2025-02-11

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

公开(公告)号：US20250048936A1

公开(公告)日：2025-02-06

申请号：US18919382

申请日：2024-10-17

Applicant: United Microelectronics Corp.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

公开(公告)号：US20250040195A1

公开(公告)日：2025-01-30

申请号：US18917979

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer and including a device region, and a charge trap layer in the substrate and extending between the insulating layer and the substrate and directly under the device region. The charge trap layer includes a plurality of n-type first doped regions and a plurality of p-type second doped regions alternately arranged and directly in contact with each other to form a plurality of interrupted depletion junctions.

公开(公告)号：US20250040180A1

公开(公告)日：2025-01-30

申请号：US18916695

申请日：2024-10-15

Applicant: United Microelectronics Corp.

Inventor： Zong-Han Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: A lateral diffused metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a second fin-shaped structure adjacent to the first fin-shaped structure, a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, a first gate structure on the first fin-shaped structure and part of the STI, a second gate structure on the second fin-shaped structure, and an air gap between the first gate structure and the second gate structure.

公开(公告)号：US20250040149A1

公开(公告)日：2025-01-30

申请号：US18916730

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.