公开(公告)号：US12272397B2

公开(公告)日：2025-04-08

申请号：US18180864

申请日：2023-03-09

Applicant: United Microelectronics Corp.

Inventor： Yi Ting Hung ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: G11C11/00 ,  G11C13/00

Abstract: A forming operation method of a resistive random access memory is provided. The method includes the following steps. A positive pulse and a negative pulse are sequentially applied, by a bit line/source line driver, to multiple resistive random access memory cells in a direction form a farthest location to a nearest location based on the bit line/source line driver through a bit line and a source line to break down a dielectric film of each of the resistive random access memory cells and generate a conductive filament of each of the resistive random access memory cells.

公开(公告)号：US20250113589A1

公开(公告)日：2025-04-03

申请号：US18979508

申请日：2024-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

公开(公告)号：US12266722B2

公开(公告)日：2025-04-01

申请号：US17207719

申请日：2021-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device and its manufacturing method, and the semiconductor device includes a substrate, a channel layer, a gate electrode, a first electrode, a second electrode, and a metal plate. The channel layer is disposed on the substrate, and the gate electrode is disposed on the channel layer. The first electrode and the second electrode are disposed on the channel layer, at two opposite sides of the gate electrode respectively. The metal plate is disposed over the channel layer, between the first electrode and the gate electrode. The metal plate includes a first extending portion and a second extending portion, wherein the second extending portion extends towards the substrate without contacting the channel layer, and the first extending portion extends toward and directly contacts the first electrode or the second electrode.

公开(公告)号：US20250107454A1

公开(公告)日：2025-03-27

申请号：US18976359

申请日：2024-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

公开(公告)号：US20250102922A1

公开(公告)日：2025-03-27

申请号：US18382528

申请日：2023-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Ruei-Jhe Tsao ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Chiu-Te Lee

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033

Abstract: The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

公开(公告)号：US12262647B2

公开(公告)日：2025-03-25

申请号：US18592553

申请日：2024-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  H10B61/00

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

公开(公告)号：US12262544B2

公开(公告)日：2025-03-25

申请号：US18595363

申请日：2024-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer, and patterning the second SOT layer and the passivation layer.

公开(公告)号：US20250098333A1

公开(公告)日：2025-03-20

申请号：US18380647

申请日：2023-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun

IPC: H01L27/02

Abstract: An ESD guard ring structure includes numerous first fin structures, numerous second fin structures, numerous first polysilicon conductive lines, numerous second polysilicon conductive lines, numerous third polysilicon conductive lines and numerous single diffusion breaks. Each of the first fin structures includes at least one single diffusion break therein. Each of the single diffusion breaks overlaps one of the third polysilicon conductive lines.

公开(公告)号：US12255245B2

公开(公告)日：2025-03-18

申请号：US18590985

申请日：2024-02-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions. A top surface of the first vertical portion in and a top surface of one of the first horizontal portions are coplanar.

公开(公告)号：US20250089349A1

公开(公告)日：2025-03-13

申请号：US18381639

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin

IPC: H01L27/06 ,  H01L21/265 ,  H01L21/762 ,  H01L29/78

Abstract: A structure with a capacitor and a fin transistor includes a substrate. The substrate includes a capacitor region and a fin transistor region. A mesa is disposed within the capacitor region of the substrate. The mesa protrudes from a surface of the substrate. The mesa includes a top surface and two sloping surfaces. Each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate. A doping region is disposed within the mesa. A capacitor electrode is only disposed on the top surface. A capacitor dielectric layer is disposed between the capacitor electrode and the doping region.