公开(公告)号：US07060865B2

公开(公告)日：2006-06-13

申请号：US10292232

申请日：2002-11-12

Applicant: Zhong Yi Ding ,  James Richardson Lattner

Inventor： Zhong Yi Ding ,  James Richardson Lattner

IPC: C07C7/04 ,  C07C7/11 ,  C07C41/42 ,  C07C41/38

CPC classification number: C07C41/38 ,  C07C41/42 ,  Y02P30/464 ,  C07C43/043

Abstract: Disclosed is a process for removing DME from a stream containing C4 olefins. The process includes providing a first stream comprising C4 olefins, C5+ hydrocarbons, DME, and methanol. The first stream is separated into a second stream comprising the C4 olefins and the DME and a third stream comprising the C5+ hydrocarbons and the methanol. The second stream is directed to a DME absorption unit, wherein the second stream contacts water under conditions effective to separate the C4 olefins from the DME. Also disclosed is a process including contacting the first stream with water in a methanol removal unit under conditions effective to separate remove the methanol therefrom; distilling the methanol-depleted stream to remove C5+ hydrocarbon components, and contacting the stream with water in a DME removal unit under conditions effective to form an overhead stream comprising the C4 olefins and a bottoms stream comprising the DME.

Abstract translation: 公开了从含有C4烯烃的流中除去DME的方法。 该方法包括提供包含C4烯烃，C5 +烃，DME和甲醇的第一流。 将第一流分离成包含C4烯烃和DME的第二料流和包含C5 +烃和甲醇的第三料流。 第二流被引导到DME吸收单元，其中第二流在有效地将C 4烯烃与DME分离的条件下与水接触。 还公开了一种方法，包括在有效分离除去甲醇的条件下，使第一流与甲醇去除单元中的水接触; 蒸馏除去甲醇的流以除去C5 +烃组分，并在有效形成包含C 4烯烃的塔顶物流和包含DME的塔底物流的条件下，在DME去除单元中使该物流与水接触。

公开(公告)号：US07027677B2

公开(公告)日：2006-04-11

申请号：US10848924

申请日：2004-05-19

Applicant: Ruolin Li ,  Ut Tran ,  Xuejun Ying ,  Jun Liu ,  Yi Ding ,  Hiroaki Fukuto

Inventor： Ruolin Li ,  Ut Tran ,  Xuejun Ying ,  Jun Liu ,  Yi Ding ,  Hiroaki Fukuto

IPC: G02B6/12

CPC classification number: G02B6/12004 ,  G02B2006/12109 ,  G02B2006/12119 ,  G02B2006/12147 ,  G02B2006/12152

Abstract: Optical components may be integrated into planar light circuits. For example, thin film filters may be integrated through trenches in planar light circuits to achieve demultiplexing of at least two multiplexed optical wavelengths. An optical waveguide may be interfaced with a laser or a light detector through a mode converter formed as a trench in the planar light circuit. The mode converter may have a curved surface to achieve mode conversion.

Abstract translation: 光学元件可以集成到平面光电路中。 例如，薄膜滤光器可以通过平面光电路中的沟槽集成，以实现至少两个复用光波长的解复用。 光波导可以通过在平面光电路中形成为沟槽的模式转换器与激光器或光检测器接口。 模式转换器可以具有曲面以实现模式转换。

公开(公告)号：US07018895B2

公开(公告)日：2006-03-28

申请号：US11102066

申请日：2005-04-08

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/7887

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160). A dielectric layer (164) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate (140). Each control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在具有多个浮动栅极（160）的存储单元（110）中，在浮置栅极之前形成选择栅极（140）。 在一些实施例中，存储器单元还具有在选择栅极之后形成的控制栅极（170）。 衬底隔离区（220）形成在半导体衬底（120）中。 衬底隔离区突出于衬底上方。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区露出。 在浮动栅极层上形成电介质（164），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些控制栅极和浮置栅极独立于光刻对准来定义。 在另一方面，非易失性存储单元具有至少两个导电浮动栅极（160）。 覆盖浮动栅极的介电层（164）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的侧壁的连续特征。 每个控制栅极（160）覆盖在电介质层的连续特征上并且也覆盖在浮动栅极上。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US07005338B2

公开(公告)日：2006-02-28

申请号：US10252143

申请日：2002-09-19

Applicant: Yi Ding ,  Vei-Han Chan

Inventor： Yi Ding ,  Vei-Han Chan

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825

Abstract: A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell's floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench. The additional dielectric can be formed with shallow trench isolation technology. The additional dielectric reduces the capacitance between the second source/drain region (130) and the floating gate.

Abstract translation: 非易失性存储单元的浮动栅极（110）形成在半导体衬底（220）中的沟槽（114）中。 电介质（128）覆盖沟槽的表面。 字线（140）具有覆盖沟槽的部分。 电池的浮栅晶体管具有第一源极/漏极区域（226），沟道区域（224）和第二源极/漏极区域（130）。 电介质（128）比在第一源极/漏极区域（122）的至少一部分附近比在沟道区域的至少一部分附近的泄漏更强。 如果编程和擦除操作不依赖于通过较强部分的电流，则附加介质的较强部分（128.1）可提高数据保持，而不会增加编程和擦除时间。 附加电介质（210）具有位于沟槽和第二源极/漏极区域（130）的顶部之间的衬底顶表面下方的部分。 第二源极/漏极区域具有位于附加电介质下方并满足沟槽的部分。 附加电介质可以用浅沟槽隔离技术形成。 附加电介质减小了第二源极/漏极区域（130）和浮动栅极之间的电容。

公开(公告)号：US20060039702A1

公开(公告)日：2006-02-23

申请号：US10921561

申请日：2004-08-19

Applicant: Jun Su ,  Yi Ding

Inventor： Jun Su ,  Yi Ding

IPC: H04J14/02

CPC classification number: H04J14/0221

Abstract: An automatic shutdown system for optical multiplexers and demultiplexers includes an optical switch that is disposed in a common optical channel between a transmitter and a receiver of an optical communication system. The optical switch may attenuate or block a signal in the common optical channel during power-off conditions. The optical switch may also provide a low insertion loss and low polarization loss in the common optical channel during power-on conditions.

Abstract translation: 用于光复用器和解复用器的自动关闭系统包括光开关，其设置在光通信系统的发射机和接收机之间的公共光信道中。 在断电条件下，光开关可能衰减或阻断公共光通道中的信号。 在开机状态下，光开关还可以在公共光通道中提供低插入损耗和低极化损耗。

公开(公告)号：US20050272205A1

公开(公告)日：2005-12-08

申请号：US11182875

申请日：2005-07-14

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/768 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11546

Abstract: A gate dielectric (150) for a gate (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate (140). The dielectric thickness on the other gate is controlled by the dopant concentration in the other gate. The gates may be gates of different MOS transistors, or a select gate and a floating gate of a memory cell. Other features are also provided.

公开(公告)号：US06962851B2

公开(公告)日：2005-11-08

申请号：US10393212

申请日：2003-03-19

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825

Abstract: In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed and the floating layer is removed from over at least a portion of the select gate lines. A dielectric (1510) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These protrusions are exploited to define the control gates independently of photolithographic alignment. The floating gates are then defined independently of any photolithographic alignment other than the alignment involved in patterning the substrate isolation regions and the select gate lines. In another aspect, a nonvolatile memory cell has a conductive floating gate (160). A dielectric layer (1510) overlying the floating gate has a continuous feature that overlies the floating gate and also overlies the select gate (140). The control gate (160) overlies the continuous feature of the dielectric layer and also overlies the floating gate but not the select gate. In another aspect, substrate isolation regions (220) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Abstract translation: 在非易失性存储器中，在半导体衬底（120）中形成衬底隔离区（220）。 衬底隔离区域是突出于衬底上方的电介质区域。 然后选择栅极线（140）。 然后沉积浮栅层（160）。 蚀刻浮栅，直到衬底隔离区被暴露，并且浮选层从至少一部分选择栅极线上去除。 在浮动栅极层上形成电介质（1510），并沉积控制栅极层（170）。 控制栅极层在每个选择栅极线上向上突出。 这些突起被利用来独立于光刻对准来限定控制栅。 然后，浮动栅极独立于除图案化衬底隔离区域和选择栅极线之外的对准的任何光刻对准。 在另一方面，非易失性存储单元具有导电浮动栅极（160）。 覆盖浮置栅极的介电层（1510）具有覆盖在浮动栅极上并且还覆盖选择栅极（140）的连续特征。 控制栅极（160）覆盖在电介质层的连续特征上，并且覆盖在浮动栅极而不是选择栅极。 在另一方面，衬底隔离区（220）形成在半导体衬底中。 选择栅极线跨越衬底隔离区。 每个选择栅线具有平坦的顶表面，但其底表面在衬底隔离区上方上下移动。 还提供其他功能。

公开(公告)号：US06951782B2

公开(公告)日：2005-10-04

申请号：US10632186

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/332

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/7887

Abstract: In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract translation: 在具有至少两个浮动栅极的非易失性存储单元中，每个浮动栅极（160）具有向上突出部分。 该部分可以形成为在选择门（140）的侧壁上的间隔物。 隔离物可以由沉积在提供浮动栅极的下部的层（160.1）之后的层（160.2）形成。 或者，向上突出部分和下部分可以由相同的层或子层形成，所有这些层或子层都存在于两个部分中。 控制栅极（170）可以在没有光刻的情况下被定义。 还提供了其他实施例。

公开(公告)号：US06902974B2

公开(公告)日：2005-06-07

申请号：US10440466

申请日：2003-05-16

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/3205 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A control gate layer (170) for a nonvolatile memory cell is formed over a select gate (140). The control gate layer protrudes upward over the select gate. An auxiliary layer (1710) is formed over the control gate layer so as to expose a protruding portion of the control gate layer. The protruding portion is processed (e.g. oxidized) to form a protective layer (1720) selectively on the control gate layer but not on the auxiliary layer. The auxiliary layer is then removed. Then the control gate layer is etched selectively to the protective layer. The protruding portion of the control gate layer is not etched away because it is protected by the protective layer. This portion provides a self-aligned control gate. The protective layer can then be removed, and a conductive material (2920), e.g. metal silicide, can be formed selectively on the protruding portion of the control gate layer in a self-aligned manner to reduce the control gate resistance. Other embodiments are also provided.

Abstract translation: 用于非易失性存储单元的控制栅极层（170）形成在选择栅极（140）上。 控制栅极层在选择栅极上向上突出。 辅助层（1710）形成在控制栅极层上，以暴露控制栅极层的突出部分。 突出部分被处理（例如氧化）以在控制栅极层上选择性地形成保护层（1720），但不在辅助层上。 然后除去辅助层。 然后将控制栅层选择性地蚀刻到保护层。 控制栅极层的突出部分不被蚀刻掉，因为它被保护层保护。 该部分提供自对准控制门。 然后可以去除保护层，并且导电材料（2920） 金属硅化物可以以自对准方式选择性地形成在控制栅极层的突出部分上，以减小控制栅极电阻。 还提供了其他实施例。

公开(公告)号：US06885044B2

公开(公告)日：2005-04-26

申请号：US10632007

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/82

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/105 ,  H01L27/11543 ,  H01L27/11546 ,  H01L29/7887 ,  H01L29/7923 ,  Y10S257/905 ,  Y10S257/909 ,  Y10S257/92

Abstract: In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.

Abstract translation: 在其中每个单元（110）具有两个浮动栅极（160）的非易失性存储器阵列中，对于任何两个连续的存储单元，一个单元的一个源极/漏极区域（174）和另一个单元的一个源极/漏极区域 的单元由形成在半导体衬底（120）中的适当导电类型（例如N型）的连续区域提供。 每个这样的连续区域仅向该列中的两个存储单元提供源极/漏极区域。 位线（180）覆盖其中形成源极/漏极区域的半导体衬底。 位线连接到源极/漏极区域。