公开(公告)号：US08487405B2

公开(公告)日：2013-07-16

申请号：US13029317

申请日：2011-02-17

Applicant: Lei Tian ,  Scott Wilson Barry ,  Xuejun Ying

Inventor： Lei Tian ,  Scott Wilson Barry ,  Xuejun Ying

IPC: H01L21/02

CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L28/90

Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.

公开(公告)号：US20050175306A1

公开(公告)日：2005-08-11

申请号：US11101320

申请日：2005-04-07

Applicant: Gabel Chong ,  Hiroaki Fukoto ,  Xuejun Ying

Inventor： Gabel Chong ,  Hiroaki Fukoto ,  Xuejun Ying

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/26 ,  G02B6/34 ,  G02B6/42 ,  G02B6/10

CPC classification number: G02B6/12019 ,  G02B6/12004 ,  G02B6/1245 ,  G02B6/266 ,  G02B6/4206 ,  G02B6/4214 ,  G02B2006/12147

Abstract: Optical waveguides with integrated collimating lenses and/or reflectors or mirrors are disclosed. The waveguides can include a convex collimating lens disposed at an end of the core. An integrated reflecting device may be inserted into the core so that at least a portion of the signal is directed upward through a convex collimating lens disposed above the upper cladding and core for power monitoring. An additional integrated reflecting device may be incorporated beyond a distal end of the core of the waveguide for power monitoring. The lenses and reflective devices or mirrors are made using reflow techniques and therefore do not require the use of separate, prefabricated components.

Abstract translation: 公开了具有集成准直透镜和/或反射镜或反射镜的光波导。 波导可以包括设置在芯的端部的凸准直透镜。 集成的反射装置可以插入到芯中，使得至少一部分信号通过设置在上包层和芯上方的凸准的准直透镜向上引导以进行功率监测。 可以将额外的集成反射装置并入到用于功率监测的波导芯的远端之外。 透镜和反射装置或镜子使用回流技术制造，因此不需要使用单独的预制部件。

公开(公告)号：US08970043B2

公开(公告)日：2015-03-03

申请号：US13018534

申请日：2011-02-01

Applicant: Quanbo Zou ,  Uppili Sridhar ,  Amit S. Kelkar ,  Xuejun Ying

Inventor： Quanbo Zou ,  Uppili Sridhar ,  Amit S. Kelkar ,  Xuejun Ying

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  C25D17/00 ,  B81C3/00 ,  C25D7/12 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L24/83 ,  B81C3/001 ,  B81C2201/0197 ,  B81C2203/035 ,  C25D7/123 ,  C25D17/001 ,  C25D17/005 ,  C25D17/007 ,  H01L23/481 ,  H01L24/13 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/13144 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/30101 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.

Abstract translation: 晶片结构包括第一晶片堆叠和设置在第一晶片堆叠上的第一结合层。 晶片结构还包括第二晶片堆叠，其包括第一表面和与第一表面相对的第二表面。 第二接合层设置在第二表面上并与第一接合层接触。 第二晶片堆叠包括从第一表面延伸到第二结合层的穿硅通孔（TSV）。 种子层设置在第一表面上并与TSV接触。

公开(公告)号：US20120194306A1

公开(公告)日：2012-08-02

申请号：US13018499

申请日：2011-02-01

Applicant: Uppili Sridhar ,  Quanbo Zou ,  Amit S. Kelkar ,  Xuejun Ying

Inventor： Uppili Sridhar ,  Quanbo Zou ,  Amit S. Kelkar ,  Xuejun Ying

IPC: H01H1/0237

CPC classification number: H01H1/0237 ,  H01H59/0009 ,  H01H2001/0084

Abstract: A micro relay of a micro-electro-mechanical system (MEMS), includes a cap substrate, a first electrical contact, an actuator, and a second electrical contact. The first electrical contact is formed on the cap substrate, includes a platinum group metal, and includes a first surface layer of an oxide of the platinum group metal. The second electrical contact is formed on the actuator, includes the platinum group metal, and includes a second surface layer of the oxide of the platinum group metal. At least a first portion of the first surface layer contacts at least a second portion of the second surface layer during cycling of the micro relay.

Abstract translation: 微电子机械系统（MEMS）的微型继电器包括盖基板，第一电触头，致动器和第二电触点。 第一电接触形成在盖基板上，包括铂族金属，并且包括铂族金属的氧化物的第一表面层。 第二电触点形成在致动器上，包括铂族金属，并且包括铂族金属的氧化物的第二表面层。 第一表面层的至少第一部分在微型继电器的循环期间接触第二表面层的至少第二部分。

公开(公告)号：US20130037948A1

公开(公告)日：2013-02-14

申请号：US13205682

申请日：2011-08-09

Applicant: Arkadii V. Samoilov ,  Tyler Parent ,  Xuejun Ying

Inventor： Arkadii V. Samoilov ,  Tyler Parent ,  Xuejun Ying

IPC: H01L23/485 ,  H01L21/28

CPC classification number: H01L24/83 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/82 ,  H01L24/92 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/17181 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/05552

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract translation: 描述了在其中形成有通孔基板通孔的半导体器件。 在一个或多个实施方案中，半导体器件包括与图案化的粘合剂材料结合在一起的顶部晶片和底部晶片。 顶部晶片和底部晶片包括形成在其中的一个或多个集成电路。 集成电路连接到布置在顶部和底部晶片的表面上的一个或多个导电层。 通过顶部晶片和图案化的粘合剂材料形成通孔，使得可以在形成在顶部晶片中的集成电路和形成在底部晶片中的集成电路之间形成电互连。 通孔包括提供顶部和底部晶片之间的电互连的导电材料。

公开(公告)号：US20120193808A1

公开(公告)日：2012-08-02

申请号：US13018534

申请日：2011-02-01

Applicant: Quanbo Zou ,  Uppili Sridhar ,  Amit S. Kelkar ,  Xuejun Ying

Inventor： Quanbo Zou ,  Uppili Sridhar ,  Amit S. Kelkar ,  Xuejun Ying

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/83 ,  B81C3/001 ,  B81C2201/0197 ,  B81C2203/035 ,  C25D7/123 ,  C25D17/001 ,  C25D17/005 ,  C25D17/007 ,  H01L23/481 ,  H01L24/13 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/13144 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/30101 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.

Abstract translation: 晶片结构包括第一晶片堆叠和设置在第一晶片堆叠上的第一结合层。 晶片结构还包括第二晶片堆叠，其包括第一表面和与第一表面相对的第二表面。 第二接合层设置在第二表面上并与第一接合层接触。 第二晶片堆叠包括从第一表面延伸到第二结合层的穿硅通孔（TSV）。 种子层设置在第一表面上并与TSV接触。

公开(公告)号：US07027677B2

公开(公告)日：2006-04-11

申请号：US10848924

申请日：2004-05-19

Applicant: Ruolin Li ,  Ut Tran ,  Xuejun Ying ,  Jun Liu ,  Yi Ding ,  Hiroaki Fukuto

Inventor： Ruolin Li ,  Ut Tran ,  Xuejun Ying ,  Jun Liu ,  Yi Ding ,  Hiroaki Fukuto

IPC: G02B6/12

CPC classification number: G02B6/12004 ,  G02B2006/12109 ,  G02B2006/12119 ,  G02B2006/12147 ,  G02B2006/12152

Abstract: Optical components may be integrated into planar light circuits. For example, thin film filters may be integrated through trenches in planar light circuits to achieve demultiplexing of at least two multiplexed optical wavelengths. An optical waveguide may be interfaced with a laser or a light detector through a mode converter formed as a trench in the planar light circuit. The mode converter may have a curved surface to achieve mode conversion.

Abstract translation: 光学元件可以集成到平面光电路中。 例如，薄膜滤光器可以通过平面光电路中的沟槽集成，以实现至少两个复用光波长的解复用。 光波导可以通过在平面光电路中形成为沟槽的模式转换器与激光器或光检测器接口。 模式转换器可以具有曲面以实现模式转换。

公开(公告)号：US20050259910A1

公开(公告)日：2005-11-24

申请号：US10848924

申请日：2004-05-19

Applicant: Ruolin Li ,  UT Tran ,  Xuejun Ying ,  Jun Liu ,  YI Ding ,  Hiroaki Fukuto

Inventor： Ruolin Li ,  UT Tran ,  Xuejun Ying ,  Jun Liu ,  YI Ding ,  Hiroaki Fukuto

IPC: G02B6/12

CPC classification number: G02B6/12004 ,  G02B2006/12109 ,  G02B2006/12119 ,  G02B2006/12147 ,  G02B2006/12152

Abstract: Optical components may be integrated into planar light circuits. For example, thin film filters may be integrated through trenches in planar light circuits to achieve demultiplexing of at least two multiplexed optical wavelengths. An optical waveguide may be interfaced with a laser or a light detector through a mode converter formed as a trench in the planar light circuit. The mode converter may have a curved surface to achieve mode conversion.

Abstract translation: 光学元件可以集成到平面光电路中。 例如，薄膜滤波器可以通过平面光电路中的沟槽集成，以实现至少两个复用的光波长的解复用。 光波导可以通过在平面光电路中形成为沟槽的模式转换器与激光器或光检测器接口。 模式转换器可以具有曲面以实现模式转换。

公开(公告)号：US08742574B2

公开(公告)日：2014-06-03

申请号：US13205682

申请日：2011-08-09

Applicant: Arkadii V. Samoilov ,  Tyler Parent ,  Xuejun Ying

Inventor： Arkadii V. Samoilov ,  Tyler Parent ,  Xuejun Ying

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/83 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/82 ,  H01L24/92 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/17181 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/245 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/05552

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract translation: 描述了在其中形成有通孔基板通孔的半导体器件。 在一个或多个实施方案中，半导体器件包括与图案化的粘合剂材料结合在一起的顶部晶片和底部晶片。 顶部晶片和底部晶片包括形成在其中的一个或多个集成电路。 集成电路连接到布置在顶部和底部晶片的表面上的一个或多个导电层。 通过顶部晶片和图案化的粘合剂材料形成通孔，使得可以在形成在顶部晶片中的集成电路和形成在底部晶片中的集成电路之间形成电互连。 通孔包括提供顶部和底部晶片之间的电互连的导电材料。

公开(公告)号：US20120211865A1

公开(公告)日：2012-08-23

申请号：US13029317

申请日：2011-02-17

Applicant: LEI TIAN ,  SCOTT WILSON BARRY ,  XUEJUN YING

Inventor： LEI TIAN ,  SCOTT WILSON BARRY ,  XUEJUN YING

IPC: H01L29/92

CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L28/90

Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.

Abstract translation: 提供了一种高密度深沟槽MIM电容器结构，其中诸如Poly-SixGe1-x的半导体材料的导电压缩共形施加的层在MIM电容器层内交错，以平衡由这些MIM电容器层产生的拉伸应力。 导电压缩共形施加材料层的交错适用于在高密度深沟槽MIM电容器硅器件的制造过程期间平衡硅晶片的凸（向上）弯曲，从而有助于使每个晶片的这种器件的生产产量最大化。