公开(公告)号：US20100123203A1

公开(公告)日：2010-05-20

申请号：US12273409

申请日：2008-11-18

申请人： Krishna Kumar Bhuwalka ,  Yi-Ming Sheu ,  Carlos H. Diaz

发明人： Krishna Kumar Bhuwalka ,  Yi-Ming Sheu ,  Carlos H. Diaz

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first conductivity type. A second source/drain region is on an opposite side of the channel region than the first source/drain region, wherein the second source/drain region is a metal region. A pocket region of a second conductivity type opposite the first conductivity type is horizontally between the channel region and the second source/drain region.

摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 以及在栅极电介质上的栅电极。 第一源极/漏极区域与栅极电介质相邻，其中第一源极/漏极区域是半导体区域并且具有第一导电类型。 第二源极/漏极区域在沟道区域的与第一源极/漏极区域相反的一侧上，其中第二源极/漏极区域是金属区域。 与第一导电类型相反的第二导电类型的口袋区域在沟道区域和第二源极/漏极区域之间是水平的。

公开(公告)号：US20080290412A1

公开(公告)日：2008-11-27

申请号：US11751959

申请日：2007-05-22

申请人： Chih-Chiang Wang ,  Yi-Ming Sheu ,  Ying-Shiou Lin

发明人： Chih-Chiang Wang ,  Yi-Ming Sheu ,  Ying-Shiou Lin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1083 ,  H01L29/66636

摘要： An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.

摘要翻译： 一种装置，包括第一掺杂剂型和第一掺杂剂浓度的衬底; 并且具有大于第一掺杂剂浓度的第一掺杂剂类型和第二掺杂剂浓度; 在所述衬底上方的栅堆叠，并且在所述袋区域之间横向; 第一和第二源极/漏极区域在栅极堆叠的相对侧上并且垂直地在栅极堆叠层与凹穴区域之间，第一和第二源极/漏极区域具有与第一掺杂剂类型相反的第二掺杂剂类型和第三掺杂剂浓度; 以及具有大于第三掺杂剂浓度的第二掺杂剂类型和第四掺杂剂浓度的第三和第四源极/漏极区域，其中所述穴状区域在第三和第四源极/漏极区域之间，并且第三和第四源极/漏极 区域在第一和第二源极/漏极区域之间以及基板的主体部分之间是垂直的。

公开(公告)号：US07371629B2

公开(公告)日：2008-05-13

申请号：US10314689

申请日：2002-12-09

申请人： Chu-Yun Fu ,  Chi-Hsun Hsieh ,  Yi-Ming Sheu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Chi-Hsun Hsieh ,  Yi-Ming Sheu ,  Syun-Ming Jang

IPC分类号： H01L21/8237

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/28247 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835

摘要： A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NH3 flow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NH3 and SiH4 flow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.

摘要翻译： 提供了一种用于改善NMOS和PMOS晶体管中的Idsat的方法。 在MOSFET制造方案中，通过PECVD技术在STI和硅化物区域和侧壁间隔物上沉积氮化硅蚀刻停止层。 在氮化物上形成介电层，然后通过电介质层和氮化物层到硅化物区域制造接触孔，并填充金属。 对于NMOS晶体管，硅烷和NH 3 3流速和400℃的温度对于改善NMOS短沟道Idsat至关重要。 氮化物中的氢含量通过较高的NH 3和SiH 4 O 3流速而增加，但不会显着降低HCE和Vt。使用PMOS晶体管，沉积温度增加到550° C.降低氢含量，提高HCE和Vt稳定性。

公开(公告)号：US07071515B2

公开(公告)日：2006-07-04

申请号：US10619114

申请日：2003-07-14

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

摘要翻译： 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US20060033158A1

公开(公告)日：2006-02-16

申请号：US11255389

申请日：2005-10-21

申请人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

发明人： Carlos Diaz ,  Yi-Ming Sheu ,  Syun-Ming Jang ,  Hun-Jan Tao ,  Fu-Liang Yang

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78621 ,  H01L29/78654

摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.

摘要翻译： 用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。 该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。 根据上述特征，以增强的性能制造场效应晶体管器件。

公开(公告)号：US06673683B1

公开(公告)日：2004-01-06

申请号：US10291029

申请日：2002-11-07

申请人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

发明人： Yi-Ming Sheu ,  Yi-Ling Chan ,  Da-Wen Lin ,  Wan-Yih Lien ,  Carlos H. Diaz

IPC分类号： H01L21336

CPC分类号： H01L29/66553 ,  H01L29/66545 ,  H01L29/6659

摘要： A method for forming a field effect transistor device within a semiconductor product employs a patterned dummy layer first as an ion implantation mask layer when forming a pair of source/drain regions, and then as a mandrel layer for forming a pair of patterned sacrificial layers which define an aperture of linewidth and location corresponding to the patterned dummy layer. A pair of sacrificial spacer layers and a gate electrode are then formed self-aligned within the aperture. The pair of patterned sacrificial layers and the pair of sacrificial spacer layers are then stripped and the gate electrode is employed as a mask for ion implanting forming a pair of lightly doped extension regions partially overlapping the pair of source/drain regions within the semiconductor substrate.

摘要翻译： 在半导体产品中形成场效应晶体管器件的方法当形成一对源极/漏极区域时首先使用图案化虚拟层作为离子注入掩模层，然后作为用于形成一对图案化牺牲层的心轴层， 限定对应于图案化虚拟层的线宽和位置的孔径。 然后在孔内自对准地形成一对牺牲间隔层和栅电极。 然后剥去一对图案化牺牲层和一对牺牲隔离层，并且使用栅电极作为用于离子注入的掩模，形成与半导体衬底内的一对源/漏区部分重叠的一对轻掺杂的延伸区。

公开(公告)号：US06670226B2

公开(公告)日：2003-12-30

申请号：US10094460

申请日：2002-03-08

申请人： Yo-Sheng Lin ,  Yi-Ming Sheu ,  Da-Wen Lin ,  Chi-Hsun Hsieh

发明人： Yo-Sheng Lin ,  Yi-Ming Sheu ,  Da-Wen Lin ,  Chi-Hsun Hsieh

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  H01L21/32115 ,  H01L21/3212

摘要： Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

公开(公告)号：US08859380B2

公开(公告)日：2014-10-14

申请号：US12944104

申请日：2010-11-11

申请人： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tsung-Hsing Yu ,  Kuan-Lun Cheng ,  Chih-Pin Tsao ,  Wen-Yuan Chen ,  Chun-Fu Cheng ,  Chih-Ching Wang

发明人： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tsung-Hsing Yu ,  Kuan-Lun Cheng ,  Chih-Pin Tsao ,  Wen-Yuan Chen ,  Chun-Fu Cheng ,  Chih-Ching Wang

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66575

摘要： A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°.

摘要翻译： 形成集成电路的方法包括：在衬底上形成沿着第一方向纵向布置的多个栅极结构。 对基板执行多个角度离子注入。 每个角度离子注入相对于第二方向具有相应的注入角度。 第二方向基本上平行于衬底的表面并且基本上与第一方向正交。 每个注入角度基本上大于0°。

公开(公告)号：US20100052065A1

公开(公告)日：2010-03-04

申请号：US12391821

申请日：2009-02-24

申请人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Anson Wang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Harry Hak-Lay Chuang ,  Shin-Puu Jeng

发明人： Carlos H. Diaz ,  Yi-Ming Sheu ,  Anson Wang ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Harry Hak-Lay Chuang ,  Shin-Puu Jeng

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7848

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.

摘要翻译： 本发明提供集成电路。 集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置，其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。

公开(公告)号：US07399679B2

公开(公告)日：2008-07-15

申请号：US11288858

申请日：2005-11-29

申请人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

发明人： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC分类号： H01L21/337 ,  H01L21/336 ,  H01L21/76 ,  H01L21/425

CPC分类号： H01L28/40 ,  H01L21/31144 ,  H01L21/76237 ,  H01L21/823481 ,  H01L27/10835 ,  H01L27/10861 ,  H01L27/1087

摘要： A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

摘要翻译： 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。