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1.
公开(公告)号:US20100052065A1
公开(公告)日:2010-03-04
申请号:US12391821
申请日:2009-02-24
申请人: Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
发明人: Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
IPC分类号: H01L27/092
CPC分类号: H01L21/823807 , H01L21/823828 , H01L27/0207 , H01L29/165 , H01L29/66628 , H01L29/7848
摘要: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.
摘要翻译: 本发明提供集成电路。 集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置,其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。
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公开(公告)号:US09349655B2
公开(公告)日:2016-05-24
申请号:US12391821
申请日:2009-02-24
申请人: Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
发明人: Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
IPC分类号: H01L21/70 , H01L21/8238 , H01L27/02 , H01L29/165 , H01L29/66 , H01L29/78
CPC分类号: H01L21/823807 , H01L21/823828 , H01L27/0207 , H01L29/165 , H01L29/66628 , H01L29/7848
摘要: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.
摘要翻译: 本发明提供集成电路。 集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置,其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。
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公开(公告)号:US08890260B2
公开(公告)日:2014-11-18
申请号:US12554604
申请日:2009-09-04
申请人: Harry Hak-Lay Chuang , Kong-Beng Thei , Sheng-Chen Chung , Chiung-Han Yeh , Lee-Wee Teo , Yu-Ying Hsu , Bao-Ru Young
发明人: Harry Hak-Lay Chuang , Kong-Beng Thei , Sheng-Chen Chung , Chiung-Han Yeh , Lee-Wee Teo , Yu-Ying Hsu , Bao-Ru Young
IPC分类号: H01L29/78 , H01L27/06 , H01L27/092 , H01L29/66 , H01L21/8238 , H01L49/02
CPC分类号: H01L29/66545 , H01L21/823842 , H01L27/0629 , H01L27/0802 , H01L27/0922 , H01L28/20 , H01L29/6659 , H01L29/7833 , H01L2223/6672
摘要: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
摘要翻译: 本发明提供集成电路。 集成电路包括半导体衬底; 以及设置在半导体衬底上的无源多晶硅器件。 无源多晶硅器件还包括多晶硅特征; 以及嵌入在多晶硅特征中的多个电极。
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公开(公告)号:US20110057267A1
公开(公告)日:2011-03-10
申请号:US12554604
申请日:2009-09-04
申请人: Harry Hak-Lay Chuang , Kong-Beng Thei , Sheng-Chen Chung , Chiung-Han Yeh , Lee-Wee Teo , Yu-Ying Hsu , Bao-Ru Young
发明人: Harry Hak-Lay Chuang , Kong-Beng Thei , Sheng-Chen Chung , Chiung-Han Yeh , Lee-Wee Teo , Yu-Ying Hsu , Bao-Ru Young
CPC分类号: H01L29/66545 , H01L21/823842 , H01L27/0629 , H01L27/0802 , H01L27/0922 , H01L28/20 , H01L29/6659 , H01L29/7833 , H01L2223/6672
摘要: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
摘要翻译: 本发明提供集成电路。 集成电路包括半导体衬底; 以及设置在半导体衬底上的无源多晶硅器件。 无源多晶硅器件还包括多晶硅特征; 以及嵌入在多晶硅特征中的多个电极。
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5.
公开(公告)号:US20120270379A1
公开(公告)日:2012-10-25
申请号:US13538220
申请日:2012-06-29
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
IPC分类号: H01L21/76
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
摘要翻译: 一种半导体器件制造方法,包括在衬底的第一部分中形成多个栅极结构,其中所述多个栅极结构具有第一高度。 第一金属栅极结构形成在衬底的第二部分中,第一金属栅极结构被隔离区包围。 在基板的第二部分中形成多个虚拟栅极结构。 多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。 多个虚拟结构具有与多个栅极结构基本平面的顶表面,并且覆盖基板的第二部分的图案密度的至少5%。
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公开(公告)号:US20120228679A1
公开(公告)日:2012-09-13
申请号:US13475245
申请日:2012-05-18
IPC分类号: H01L29/78 , H01L21/336
CPC分类号: H01L29/78 , H01L21/28247 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要: Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region.
摘要翻译: 公开了在接触形成期间保护栅极结构的各种方法。 一种示例性方法包括:在衬底上形成栅极结构,其中栅极结构包括栅极,栅极结构插入设置在衬底中的源极区域和漏极区域; 图案化第一蚀刻停止层,使得第一蚀刻停止层设置在源极区域和漏极区域上; 图案化第二蚀刻停止层,使得第二蚀刻停止层设置在栅极结构上; 以及形成源极接触,漏极接触和栅极接触,其中所述源极接触和所述漏极接触延伸穿过所述第一蚀刻停止层,并且所述栅极接触延伸穿过所述第二蚀刻停止层,其中形成所述源极接触, 漏极接触,并且栅极接触包括同时移除第一蚀刻停止层和第二蚀刻停止层以暴露栅极,源极区域和漏极区域。
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公开(公告)号:US20100052060A1
公开(公告)日:2010-03-04
申请号:US12455509
申请日:2009-06-03
申请人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
发明人: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
CPC分类号: H01L21/823437 , H01L21/31053 , H01L21/3212 , H01L21/823828 , H01L27/08
摘要: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.
摘要翻译: 提供一种半导体器件,其包括具有第一部分和第二部分的半导体衬底,形成在衬底的第一部分中的晶体管,每个晶体管具有具有高k电介质和金属栅极的栅极结构,形成器件元件 在衬底的第二部分中,器件元件被隔离区域隔离,抛光停止件形成在隔离区域附近,并且具有与第一区域中的晶体管的栅极结构的表面基本平面的表面。
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公开(公告)号:US08476126B2
公开(公告)日:2013-07-02
申请号:US12702012
申请日:2010-02-08
IPC分类号: H01L21/338 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/283
CPC分类号: H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7833 , H01L29/7834
摘要: A method for fabricating an integrated circuit device is disclosed. An exemplary method includes providing a substrate; forming a high-k dielectric layer over the substrate; forming a first capping layer over the high-k dielectric layer; forming a second capping layer over the first capping layer; forming a dummy gate layer over the second capping layer; performing a patterning process to form a gate stack including the high-k dielectric layer, first and second capping layers, and dummy gate layer; removing the dummy gate layer from the gate stack, thereby forming an opening that exposes the second capping layer; and filling the opening with a first metal layer over the exposed second capping layer and a second metal layer over the first metal layer, wherein the first metal layer is different from the second metal layer and has a work function suitable to the semiconductor device.
摘要翻译: 公开了一种用于制造集成电路器件的方法。 一种示例性方法包括提供基底; 在衬底上形成高k电介质层; 在所述高k电介质层上形成第一覆盖层; 在所述第一覆盖层上形成第二覆盖层; 在所述第二封盖层上形成虚拟栅极层; 执行图案化处理以形成包括高k电介质层,第一和第二封盖层以及虚拟栅极层的栅极堆叠; 从所述栅极堆叠中去除所述伪栅极层,从而形成暴露所述第二封盖层的开口; 以及在所述暴露的第二覆盖层上方的第一金属层和所述第一金属层上的第二金属层填充所述开口,其中所述第一金属层与所述第二金属层不同,并且具有适合于所述半导体器件的功函数。
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公开(公告)号:US20100270627A1
公开(公告)日:2010-10-28
申请号:US12428011
申请日:2009-04-22
CPC分类号: H01L29/78 , H01L21/28247 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.
摘要翻译: 公开了一种制造半导体器件的方法。 该方法包括提供基板; 在所述衬底上形成至少一个栅极结构; 在所述衬底中形成多个掺杂区域; 在衬底上形成蚀刻停止层; 去除所述蚀刻停止层的第一部分,其中所述蚀刻停止层的第二部分保留在所述多个掺杂区域上; 在衬底上形成硬掩模层; 去除所述硬掩模层的第一部分,其中所述硬掩模层的第二部分保留在所述至少一个栅极结构上; 以及通过所述硬掩模层的所述第二部分形成到所述至少一个栅极结构的第一接触,以及通过所述蚀刻停止层的所述第二部分到所述多个掺杂区域的第二接触。
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公开(公告)号:US08497169B2
公开(公告)日:2013-07-30
申请号:US13475245
申请日:2012-05-18
IPC分类号: H01L21/8238
CPC分类号: H01L29/78 , H01L21/28247 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要: Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region.
摘要翻译: 公开了在接触形成期间保护栅极结构的各种方法。 一种示例性方法包括:在衬底上形成栅极结构,其中栅极结构包括栅极,栅极结构插入设置在衬底中的源极区域和漏极区域; 图案化第一蚀刻停止层,使得第一蚀刻停止层设置在源极区域和漏极区域上; 图案化第二蚀刻停止层,使得第二蚀刻停止层设置在栅极结构上; 以及形成源极接触,漏极接触和栅极接触,其中所述源极接触和所述漏极接触延伸穿过所述第一蚀刻停止层,并且所述栅极接触延伸穿过所述第二蚀刻停止层,其中形成所述源极接触, 漏极接触,并且栅极接触包括同时移除第一蚀刻停止层和第二蚀刻停止层以暴露栅极,源极区域和漏极区域。
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