公开(公告)号：US20050229087A1

公开(公告)日：2005-10-13

申请号：US11105922

申请日：2005-04-13

Applicant: Sunghwan Kim ,  Yong-June Kim ,  Jong-Seon No ,  Sang-Hyun Lee ,  Yun-Hee Kim ,  Jae-Young Ahn

Inventor： Sunghwan Kim ,  Yong-June Kim ,  Jong-Seon No ,  Sang-Hyun Lee ,  Yun-Hee Kim ,  Jae-Young Ahn

IPC: G06F11/00 ,  H03M13/00 ,  H03M13/11

CPC classification number: H03M13/6356 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/6362

Abstract: Disclosed is a decoding apparatus for LDPC (Low-Density Parity-Check) codes when receiving data encoded with LDPC codes on a channel having consecutive output values, and a method thereof. The decoding method for LDPC codes uses sequential decoding and includes: (a) dividing nodes into check nodes for a parity-check message and variable nodes for a bit message according to a parity-check matrix; (b) dividing the check nodes into a predetermined number of subsets; (c) sequentially decoding the LDPC codeword of each subset for all the check nodes; (d) generating an output message for verifying validity of the decoding result; and (e) iteratively performing the steps (b), (c), and (d) by a predetermined number of iterations.

Abstract translation: 公开了一种在具有连续输出值的信道上接收用LDPC码编码的数据时的LDPC（低密度奇偶校验）码的解码装置及其方法。 LDPC码的解码方法使用顺序解码，并且包括：（a）根据奇偶校验矩阵将节点划分成用于奇偶校验消息的校验节点和用于位消息的可变节点; （b）将校验节点划分成预定数量的子集; （c）对于所有校验节点顺序解码每个子集的LDPC码字; （d）生成用于验证解码结果的有效性的输出消息; 和（e）以预定次数的迭代迭代地执行步骤（b），（c）和（d）。

公开(公告)号：US08984036B2

公开(公告)日：2015-03-17

申请号：US13547212

申请日：2012-07-12

Applicant: Yong June Kim ,  Jung Soo Chung ,  Jun Jin Kong ,  Hongrak Son

Inventor： Yong June Kim ,  Jung Soo Chung ,  Jun Jin Kong ,  Hongrak Son

IPC: G06F7/58

CPC classification number: G06F7/582

Abstract: A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area.

Abstract translation: 用于操作控制器的方法可以包括将从PN序列发生器提供的伪噪声（PN）序列存储在种子表的第i个区域中，并将PN序列从第i个区域循环移位到第（i + 1个） ）表中的区域形成表。 该表可能包括行和列区域。 用于操作控制器的方法可以包括从序列发生器接收序列，将序列分解成种子单元，将分离序列存储在种子表的第j个区域中，以及形成包括与分离序列相对应的种子单元的表 存储在第j个区域。 用于操作控制器的方法可以包括将从序列生成器提供的序列存储在包括多个区域的种子表中，并且将表中的序列循环移位，直到在每个区域中形成种子。

公开(公告)号：US08595601B2

公开(公告)日：2013-11-26

申请号：US13011279

申请日：2011-01-21

Applicant: Yong June Kim ,  Junjin Kong ,  KyoungLae Cho

Inventor： Yong June Kim ,  Junjin Kong ,  KyoungLae Cho

IPC: H03M13/00

CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/349

Abstract: Methods of operating nonvolatile memory devices include testing a plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings. An identity of the at least one weak string may be stored as weak column information. This weak column information may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on a first plurality of bits of data read from the plurality of strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits.

Abstract translation: 操作非易失性存储器设备的方法包括测试存储器件中的多个非易失性存储单元串，以识别其中具有相对于多个字符串中的其他字符串产生错误读取数据错误的较高概率的至少一个弱字符串。 至少一个弱字符串的身份可以存储为弱列信息。 该弱列信息可以用于促进错误检测和校正操作。 特别地，可以使用这样的算法对从多个串读取的数据的第一多个位进行纠错操作，所述算法基于在第一多个数据位中修改一个或多个数据位的可靠性的加权，该算法基于 弱列信息。 更具体地，可以使用一种算法，其将从至少一个弱串读取的数据位解释为相对于第一多个数据位中的其他数据位具有相对降低的可靠性。

公开(公告)号：US08522124B2

公开(公告)日：2013-08-27

申请号：US13069834

申请日：2011-03-23

Applicant: Yong-June Kim ,  Jun-Jin Kong ,  Young-Hwan Lee ,  Jae-Hong Kim

Inventor： Yong-June Kim ,  Jun-Jin Kong ,  Young-Hwan Lee ,  Jae-Hong Kim

IPC: G06F11/00 ,  H03M13/00

CPC classification number: G06F11/1048

Abstract: An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.

Abstract translation: 错误控制编码（ECC）电路包括第一解码器，第二解码器和控制器。 第一解码器接收包括第一奇偶校验和第二奇偶校验的编码数据。 第一解码器通过使用第一奇偶校验将编码数据解码为第一代码。 第二解码器连接到第一解码器。 第二解码器被配置为当第一解码器被去激活时解码编码数据，并且当第一解码器被去激活时使用第二奇偶校验解码第一代码。 控制器向第一解码器和第二解码器发送控制信号以控制第一解码器和第二解码器。

公开(公告)号：US08510624B2

公开(公告)日：2013-08-13

申请号：US12687666

申请日：2010-01-14

Applicant: Jaehong Kim ,  Junjin Kong ,  Yong June Kim

Inventor： Jaehong Kim ,  Junjin Kong ,  Yong June Kim

IPC: H03M13/00 ,  H03M13/03 ,  H04Q1/20 ,  H04L27/00

CPC classification number: G06F11/10 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  H03M13/2957

Abstract: A data processing system includes a memory configured to receive data and an encoder configured to encode data being transferred to the memory. The encoder includes an outer encoder configured to generate an outer codeword by encoding the data being transferred to the memory, and an inner encoder configured to generate a plurality of inner codewords by encoding the outer codeword.

Abstract translation: 数据处理系统包括被配置为接收数据的存储器和被配置为对传送到存储器的数据进行编码的编码器。 编码器包括：外部编码器，其被配置为通过对正被传送到存储器的数据进行编码来产生外部码字;以及内部编码器，被配置为通过对外部码字进行编码来生成多个内部码字。

公开(公告)号：USRE44421E1

公开(公告)日：2013-08-06

申请号：US13233476

申请日：2011-09-15

Applicant: Sunghwan Kim ,  Yong-June Kim ,  Jong-Seon No ,  Sang-Hyun Lee ,  Yun-Hee Kim ,  Jae-Young Ahn

Inventor： Sunghwan Kim ,  Yong-June Kim ,  Jong-Seon No ,  Sang-Hyun Lee ,  Yun-Hee Kim ,  Jae-Young Ahn

IPC: H03M13/00

CPC classification number: H03M13/6356 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/6362

Abstract: Disclosed is a decoding apparatus for LDPC (Low-Density Parity-Check) codes when receiving data encoded with LDPC codes on a channel having consecutive output values, and a method thereof. The decoding method for LDPC codes uses sequential decoding and includes the following steps: (a) the nodes are divided according to a parity-check matrix into check nodes for a parity-check message and variable nodes for a bit message; (b) the check nodes are divided into a predetermined number of subsets; (c) the LDPC codeword of each subset for all the check nodes is sequentially decoded; (d) an output message is generated for verifying validity of the decoding result; and (e) the steps (b), (c), and (d) are iteratively performed by a predetermined number of iterations.

公开(公告)号：US08432735B2

公开(公告)日：2013-04-30

申请号：US12832220

申请日：2010-07-08

Applicant: Yong June Kim ,  Jae hong Kim ,  Ki jun Lee

Inventor： Yong June Kim ,  Jae hong Kim ,  Ki jun Lee

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C7/1012 ,  G11C11/5642 ,  G11C2211/5647

Abstract: A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line.

Abstract translation: 一种对非易失性存储器件进行编程的方法包括以输入数据为单位对多个状态对进行计数，调制输入数据的单位以减少其中包含的状态对的数量，并将输入数据的调制单元编程在非易失性存储器 设备。 每个状态对包括具有第一状态并被指定用于在连接到第一字线的存储器单元中进行编程的数据，以及具有第二状态并被指定用于在连接到与第一字线相邻的第二字线的存储器单元中编程的数据 。 连接到第一字线的存储单元与连接到第二字线的存储单元相邻。

公开(公告)号：US08179718B2

公开(公告)日：2012-05-15

申请号：US12318560

申请日：2008-12-31

Applicant: Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Yong June Kim

Inventor： Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Yong June Kim

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C29/00 ,  G11C2211/5621

Abstract: Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from among the plurality of multi-level cells in which the first data page is programmed; an error analysis unit that analyzes read error information corresponding to the first data page based on a read voltage level to determine whether to correct a read error based on the analyzed read error information; and a controller that adjusts the read voltage level of the first data page depending on the determination result. Through this, it is possible to reduce an error occurrence when reading and/or programming a data page.

Abstract translation: 提供的是存储器件和存储器编程方法。 存储器件可以包括：多级单元阵列，其包括多个多电平单元; 编程单元，其对所述多个多电平单元中的第一数据页进行编程，并从所述第一数据页被编程的所述多个多电平单元中编程多电平单元中的第二数据页; 误差分析单元，其基于读取电压电平分析与所述第一数据页相对应的读取错误信息，以基于所分析的读取错误信息来确定是否校正读取错误; 以及控制器，其根据确定结果调整第一数据页的读取电压电平。 通过这种方式，可以在读取和/或编程数据页时减少错误发生。

公开(公告)号：US08059467B2

公开(公告)日：2011-11-15

申请号：US12382351

申请日：2009-03-13

Applicant: Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

Inventor： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

Abstract: Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

Abstract translation: 提供存储器件和/或存储器编程方法。 存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线 来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。 由此，可以减小存储单元的阈值电压分布的宽度。

公开(公告)号：US20110209031A1

公开(公告)日：2011-08-25

申请号：US13011279

申请日：2011-01-21

Applicant: Yong June Kim ,  Junjin Kong ,  KyoungLae Cho

Inventor： Yong June Kim ,  Junjin Kong ,  KyoungLae Cho

IPC: H03M13/05 ,  G11C16/06 ,  G06F11/10

CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/349

Abstract: Methods of operating nonvolatile memory devices include testing a plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings. An identity of the at least one weak string may be stored as weak column information. This weak column information may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on a first plurality of bits of data read from the plurality of strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits.

Abstract translation: 操作非易失性存储器设备的方法包括测试存储器件中的多个非易失性存储单元串，以识别其中具有相对于多个字符串中的其他字符串产生错误读取数据错误的较高概率的至少一个弱字符串。 至少一个弱字符串的身份可以存储为弱列信息。 该弱列信息可以用于促进错误检测和校正操作。 特别地，可以使用这样的算法对从多个串读取的数据的第一多个位进行纠错操作，所述算法基于在第一多个数据位中修改一个或多个数据位的可靠性的加权，该算法基于 弱列信息。 更具体地，可以使用一种算法，其将从至少一个弱串读取的数据位解释为相对于第一多个数据位中的其他数据位具有相对降低的可靠性。