公开(公告)号：US09495518B2

公开(公告)日：2016-11-15

申请号：US13407333

申请日：2012-02-28

Applicant: Yong June Kim ,  Hong Rak Son ,  Jae Hong Kim ,  Sang Yong Yoon ,  Ki Jun Lee ,  Jung Soo Chung ,  Seong Hyeog Choi

Inventor： Yong June Kim ,  Hong Rak Son ,  Jae Hong Kim ,  Sang Yong Yoon ,  Ki Jun Lee ,  Jung Soo Chung ,  Seong Hyeog Choi

IPC: G06F12/00 ,  G06F21/00 ,  G06F12/14 ,  G11C11/00 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  G06F11/10

CPC classification number: G06F21/00 ,  G06F11/1012 ,  G06F11/108 ,  G06F12/00 ,  G06F12/14 ,  G11C11/00 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418

Abstract: An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.

Abstract translation: 一种用于从非易失性存储器读取的装置和方法，由此使用软判决数据来确定硬判决数据的可靠性。 从非易失性存储器读取的硬判决数据被去随机化，并且从非易失性存储器读取的软判决数据不被去随机化。 使用软判决数据，硬判决数据被解码。

公开(公告)号：US09158500B2

公开(公告)日：2015-10-13

申请号：US13537297

申请日：2012-06-29

Applicant: Ki Jun Lee ,  Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim ,  Hong Rak Son ,  Jung Soo Chung ,  Seong Hyeong Choi

Inventor： Ki Jun Lee ,  Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim ,  Hong Rak Son ,  Jung Soo Chung ,  Seong Hyeong Choi

IPC: G06F7/58

CPC classification number: G06F7/584 ,  G06F2207/583

Abstract: A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.

Abstract translation: 一种数据处理装置，包括转换电路和包括多个移位寄存器的串联连接的伪随机数发生器。 转换电路从除串行连接的最后一个移位寄存器之外的多个移位寄存器中的一个的输出接收伪随机数序列，并且使用接收到的伪随机数序列将第一数据转换为第二数据。

公开(公告)号：US08972775B2

公开(公告)日：2015-03-03

申请号：US12453163

申请日：2009-04-30

Applicant: Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Kyoung Lae Cho

Inventor： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Kyoung Lae Cho

IPC: G06F11/07 ,  G11C16/10 ,  G06F11/10 ,  G11C11/56 ,  G11C16/34 ,  G11C29/00

CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.

Abstract translation: 提供了存储器件和/或管理存储器数据错误的方法。 存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。 存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。 存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。 由此，可以增加存储装置的数据的保持期。

公开(公告)号：US08812942B2

公开(公告)日：2014-08-19

申请号：US12944807

申请日：2010-11-12

Applicant: Jaehong Kim ,  Hee-Seok Eun ,  Ki-Jun Lee ,  Yong-June Kim

Inventor： Jaehong Kim ,  Hee-Seok Eun ,  Ki-Jun Lee ,  Yong-June Kim

IPC: G06F11/00

CPC classification number: G06F12/0607 ,  G06F2212/7208

Abstract: An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.

Abstract translation: 交错装置可以包括：第一缓冲器单元，被配置为以具有扇区大小的单位缓冲输入数据以产生扇区单元数据;编码单元，被配置为对扇区单元数据进行编码，并且基于编码生成多个奇偶校验码， 第二缓冲器单元，被配置为交织扇区单元数据和奇偶校验码，并且基于交织产生交织数据，第二缓冲单元包括被配置为存储交织数据的多个输出缓冲器，以及输出单元，其被配置为输出交织 数据。

公开(公告)号：US08751900B2

公开(公告)日：2014-06-10

申请号：US13106892

申请日：2011-05-13

Applicant: Yong June Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong ,  Yongtaew Yim ,  Jaehong Kim ,  KyoungLae Cho ,  Wootae Chang

Inventor： Yong June Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong ,  Yongtaew Yim ,  Jaehong Kim ,  KyoungLae Cho ,  Wootae Chang

IPC: G11C29/00 ,  H03M13/00

CPC classification number: G06F11/106 ,  H03M13/1102 ,  H03M13/136 ,  H03M13/152 ,  H03M13/155 ,  H03M13/2909 ,  H03M13/618

Abstract: A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.

Abstract translation: 存储装置包括从源区域输出读取数据的非易失性存储器装置和被配置为对读取数据中的多个向量执行ECC操作并将经纠错的读取数据写入到目标区域中的存储器控​​制器 非易失性存储器件。 存储器控制器声明对应于清洁区域的矢量是在纠错操作期间不使用多个矢量中的标志位的解码通过。

公开(公告)号：US08713411B2

公开(公告)日：2014-04-29

申请号：US12232258

申请日：2008-09-12

Applicant: Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

Inventor： Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

IPC: H03M13/00

CPC classification number: H03M13/03 ,  G06F11/1072 ,  H03M13/05

Abstract: Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.

Abstract translation: 可以提供编码/解码存储器件及其方法。 根据示例实施例的存储器件可以包括存储单元阵列和包括解码器和编码器中的至少一个的处理器。 处理器可以被配置为调整每个通道的冗余信息速率，其中每个通道是存储单元阵列的路径，数据从存储单元阵列的至少一个存储和读取。 可以通过基于来自先前码字的信息生成至少一个码字来调整冗余信息速率。 因此，示例性实施例可以减少当数据从存储器件读取并写入存储器件时的错误率。

公开(公告)号：US08711618B2

公开(公告)日：2014-04-29

申请号：US13190913

申请日：2011-07-26

Applicant: Seong Hyeog Choi ,  Hong Rak Son ,  Jun Jin Kong ,  Yong June Kim

Inventor： Seong Hyeog Choi ,  Hong Rak Son ,  Jun Jin Kong ,  Yong June Kim

IPC: G11C7/10

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10

Abstract: A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell.

Abstract translation: 一种对包含在备用区域中的多级单元进行编程的方法，所述方法包括在第一多级单元中编程第一页数据和至少一个第一虚拟数据; 以及在第二多级单元中编程第二页数据和至少一个第二伪数据。

公开(公告)号：US08587997B2

公开(公告)日：2013-11-19

申请号：US13016063

申请日：2011-01-28

Applicant: Jaehong Kim ,  Kijun Lee ,  Yong June Kim ,  Heeseok Eun

Inventor： Jaehong Kim ,  Kijun Lee ,  Yong June Kim ,  Heeseok Eun

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/26

Abstract: Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols.

Abstract translation: 提供了一种存储器系统及其操作方法。 操作方法用不同的读取电压至少一次读取观察存储器单元以配置第一读取数据符号，至少用不同的读取电压读取与观察存储器单元相邻的多个干扰存储器单元以配置第二读取数据 符号，并且基于第一读取数据符号和第二读取数据符号确定观察存储器单元的逻辑值。

公开(公告)号：US08422291B2

公开(公告)日：2013-04-16

申请号：US12662329

申请日：2010-04-12

Applicant: Yong June Kim ,  Heeseok Eun ,  Han Woong Yoo ,  Jaehong Kim ,  Hong Rak Son

Inventor： Yong June Kim ,  Heeseok Eun ,  Han Woong Yoo ,  Jaehong Kim ,  Hong Rak Son

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/00

Abstract: The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution.

Abstract translation: 存储装置包括：被配置为存储数据的存储单元;错误控制单元，被配置为根据至少一个读取级别校正从存储单元读出的数据的错误;以及读取级别控制单元，被配置为至少控制 一个读取级别，当错误是不可校正的。 读取级别控制单元被配置为测量存储单元的存储器单元的分布，被配置为过滤所测量的分布，并且被配置为基于滤波的分布来重置所述至少一个读取级别。

公开(公告)号：US20130031443A1

公开(公告)日：2013-01-31

申请号：US13550133

申请日：2012-07-16

Applicant: Eun-Chu Oh ,  Jae-Hong Kim ,  Yong-June Kim ,  Jun-Jin Kong

Inventor： Eun-Chu Oh ,  Jae-Hong Kim ,  Yong-June Kim ,  Jun-Jin Kong

IPC: G06F11/16 ,  G06F12/00

CPC classification number: G11C16/3418 ,  G06F11/1048 ,  G06F12/0246 ,  G06F2212/7205 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/349 ,  G11C2211/5644

Abstract: A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages.

Abstract translation: 操作存储器控制器的方法包括从存储器件的第一块读取数据; 从所述第一块的多个页面检测退化的页面，并对所述第一块中的所述劣化页面的数量进行计数; 并且基于所计算的劣化页面的数量来对包括退化页面的第一块进行再充电或回收。