公开(公告)号：US20090046531A1

公开(公告)日：2009-02-19

申请号：US12111468

申请日：2008-04-29

申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

IPC分类号： G11C7/04

CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

公开(公告)号：US07486576B2

公开(公告)日：2009-02-03

申请号：US11826367

申请日：2007-07-13

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Young-Hun Seo

IPC分类号： G11C7/00

CPC分类号： G11C11/4078 ,  G11C7/24

摘要： A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

摘要翻译： 包括具有用于存储数据信息的存储单元的DRAM内核的动态随机存取存储器（DRAM）装置以及在上电期间防止存储在存储单元中的数据在读取电源时被读出的读保护单元。

公开(公告)号：US20080185676A1

公开(公告)日：2008-08-07

申请号：US12078967

申请日：2008-04-09

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for forming a STI of a semiconductor device includes steps of sequentially forming a pad oxide film and a pad nitride film on the semiconductor device and carrying out a pattern process PR; etching the pad oxide film and the nitride film and carrying out a cleaning process; selectively growing epitaxial silicon; and carrying out liner oxidation on the epitaxial silicon and carrying out CMP so as to form an oxidation fill and STI.

公开(公告)号：US07294555B2

公开(公告)日：2007-11-13

申请号：US10722295

申请日：2003-11-25

申请人： Young-Hun Seo

发明人： Young-Hun Seo

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/3065 ,  H01L21/3081

摘要： A method of forming a trench in a semiconductor device includes forming a polish stop layer on a semiconductor substrate. The polish stop layer and the semiconductor substrate are then etched to form a trench. The semiconductor substrate is etched to a predetermined depth. Also, etching is performed such that ends of the polish stop layer adjacent to the trench are rounded. Next, an insulation layer that fills the trench is formed.

摘要翻译： 在半导体器件中形成沟槽的方法包括在半导体衬底上形成抛光停止层。 然后对抛光停止层和半导体衬底进行蚀刻以形成沟槽。 半导体衬底被蚀刻到预定深度。 此外，进行蚀刻，使得与沟槽相邻的抛光停止层的端部是圆形的。 接下来，形成填充沟槽的绝缘层。

公开(公告)号：US20070153590A1

公开(公告)日：2007-07-05

申请号：US11567826

申请日：2006-12-07

申请人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

发明人： Young-Hun Seo ,  Dong-Il Seo ,  Kyu-Chan Lee ,  Jong-Hyun Choi

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes, a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuits and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated white the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

摘要翻译： 一种内部参考电压发生电路，其将待机电流和半导体存储器件的引脚数量减少，其中参考电压被提供给通过连接有管芯发送器电阻器的输入接收信号的输入缓冲器， 包括：通过电源电压输出所述参考电压的分压电路; 连接到分压电路的一端的下拉驱动器; 以及校准控制电路，其比较输入的电压电平和分压电路的端部的电压电平，并根据比较的结果控制下拉驱动器的导通电阻值。 内部参考电压产生电路白色运行，存储器控制器将信号输入到模式寄存器组（MRS）中以使能内部参考电压产生电路，并且MRS的输出信号被激活。

公开(公告)号：US20070098041A1

公开(公告)日：2007-05-03

申请号：US11459312

申请日：2006-07-21

申请人： Young-Hun Seo

发明人： Young-Hun Seo

IPC分类号： G01K7/00

CPC分类号： G01K7/00 ,  G01K7/01 ,  Y10S323/907

摘要： A temperature sensor includes a proportional to absolute temperature (PTAT) current generator configured to generate a first current proportional to temperature, a first complementary to absolute temperature (CTAT) current generator configured to generate a second current inversely proportional to temperature, a second CTAT current generator configured to generate a third current inversely proportional to temperature, and a temperature sensing unit configured to convert the first current, the second current, and the third current into a signal related to the temperature.

摘要翻译： 温度传感器包括与绝对温度（PTAT）电流发生器成比例的配置以产生与温度成比例的第一电流，第一互补绝对温度（CTAT）电流发生器被配置为产生与温度成反比的第二电流，第二CTAT电流 发生器，其被配置为产生与温度成反比的第三电流;以及温度感测单元，其被配置为将所述第一电流，所述第二电流和所述第三电流转换为与所述温度相关的信号。

公开(公告)号：US07153748B2

公开(公告)日：2006-12-26

申请号：US11027539

申请日：2004-12-30

申请人： Young-Hun Seo

发明人： Young-Hun Seo

IPC分类号： H01L21/336

CPC分类号： H01L29/66606 ,  H01L29/66545 ,  H01L29/66628

摘要： Semiconductor devices having an elevated contact region and methods of fabricating the same are disclosed. A disclosed semiconductor device includes a semiconductor substrate, a gate on the semiconductor substrate, spacers on sidewalls of the gate, an epitaxial layer on the semiconductor substrate, source/drain regions within the semiconductor substrate below the epitaxial layer, and low doping concentration regions within the semiconductor below the spacers. In an example, the spacers partially overlap onto the epitaxial layer.

摘要翻译： 公开了具有升高的接触区域的半导体器件及其制造方法。 所公开的半导体器件包括半导体衬底，半导体衬底上的栅极，栅极的侧壁上的间隔物，半导体衬底上的外延层，外延层下面的半导体衬底内的源极/漏极区域和内部的低掺杂浓度区域 半导体下方的间隔物。 在一个示例中，间隔物部分地重叠到外延层上。

公开(公告)号：US07148117B2

公开(公告)日：2006-12-12

申请号：US11026232

申请日：2004-12-29

申请人： Young Hun Seo

发明人： Young Hun Seo

IPC分类号： H01L21/20

CPC分类号： H01L21/76232

摘要： Methods for forming STI structures in semiconductor devices are disclosed. A disclosed method comprises: forming a buffer oxide layer on a silicon substrate; implanting ions into the entire surface of the resulting structure and removing the buffer oxide layer; depositing a gate oxide layer, a polysilicon layer and a nitride layer, forming a photoresist pattern; forming the trench of the STI structure by perform an etching process using the photoresist pattern as an etching mask; forming a thin oxide layer inside the trench and on the nitride layer on the entire surface of the resulting structure; filling the trench with an insulating layer; planarizing the insulating layer by performing a CMP process using the nitride layer as an etching stop layer; performing a recessing process to etch the planarized insulating layer and the thin oxide layer on the trench to a predetermined depth; forming a photoresist pattern on the nitride layer; and forming the gate electrodes by performing an etching process using the photoresist pattern as a mask pattern.

摘要翻译： 公开了在半导体器件中形成STI结构的方法。 所公开的方法包括：在硅衬底上形成缓冲氧化物层; 将离子注入所得结构的整个表面并除去缓冲氧化物层; 沉积栅极氧化物层，多晶硅层和氮化物层，形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模进行蚀刻工艺来形成STI结构的沟槽; 在所述结构的整个表面上在所述沟槽内和所述氮化物层上形成薄氧化物层; 用绝缘层填充沟槽; 通过使用氮化物层作为蚀刻停止层进行CMP处理来平坦化绝缘层; 执行凹陷处理以将沟槽上的平坦化绝缘层和薄氧化物层蚀刻到预定深度; 在氮化物层上形成光致抗蚀剂图案; 以及通过使用光致抗蚀剂图案作为掩模图案进行蚀刻处理来形成栅电极。

公开(公告)号：US20060176079A1

公开(公告)日：2006-08-10

申请号：US11348582

申请日：2006-02-06

申请人： Jong-Hyun Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Young-Hun Seo

IPC分类号： H03K19/0175

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/0005

摘要： An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.

摘要翻译： 一种用于半导体存储器件的输入/输出电路，包括数据输出电路，配置为响应于输入/输出使能信号缓冲半导体存储器件中的输出数据，以将缓冲的输出数据输出到输入/输出信号线， 数据输入电路，被配置为从输入/输出信号线接收输入数据并缓冲输入数据以将缓冲的输入数据传送到半导体存储器件;以及负载控制器，被配置为响应于控制输入/输出信号线上的负载 到输入/输出使能信号。

公开(公告)号：US07002872B2

公开(公告)日：2006-02-21

申请号：US10676996

申请日：2003-09-30

申请人： Hyong-ryol Hwang ,  Young-hun Seo ,  Jae-yoon Sim

发明人： Hyong-ryol Hwang ,  Young-hun Seo ,  Jae-yoon Sim

IPC分类号： G11C8/00

CPC分类号： G11C5/063

摘要： A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.

摘要翻译： 半导体存储器件包括具有子阵列和读出放大器区域的核心块。 第一和第二电荷存储区域设置在芯块的侧面。 分别在第一和第二电荷存储区域形成第一和第二去耦电容器。 设置多个第一电压供应线，以将电源电压提供给感测放大器区域，并且连接到第一和第二去耦电容器中的每一个的一个电极。 设置多个第二电压供给线，以将接地电压提供给读出放大器区域，并连接到第一和第二去耦电容器中的每一个的另一个电极。