公开(公告)号：US20230130354A1

公开(公告)日：2023-04-27

申请号：US17512109

申请日：2021-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL ,  RAJA SWAMINATHAN

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00

Abstract: A three-dimensional semiconductor package assembly includes a die. The die includes a plurality of through silicon vias (TSVs). The TSVs includes a first TSV and a second TSV. The first TSV supplies power from an active surface of the die to a back surface of the die. The assembly also includes a passive device coupled to the back surface of the die such that conductive contacts of the passive device electrically interface with the TSVs. The first passive device receives power through the first TSV and supplies power to the first die through the second TSV.

公开(公告)号：US20220415723A1

公开(公告)日：2022-12-29

申请号：US17360834

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL ,  DEAN GONZALES

IPC: H01L21/66 ,  H01L23/498 ,  H01L21/48

Abstract: A chip for wafer-level testing of fanout chiplet, including: a die; a carrier substrate; a plurality of redistribution layers applied to the carrier substrate; and one or more first conductive pathways in the plurality of redistribution layers, wherein the one or more first conductive pathways each comprise a first end coupled to a corresponding input/output connection point of the die and a second end coupled to a corresponding probing site, wherein the one or more first conductive pathways are not routed through the carrier substrate.

公开(公告)号：US20220342165A1

公开(公告)日：2022-10-27

申请号：US17361033

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BRETT P. WILKERSON ,  RAJA SWAMINATHAN ,  KONG TOON NG ,  RAHUL AGARWAL

IPC: G02B6/42

Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

公开(公告)号：US20220319871A1

公开(公告)日：2022-10-06

申请号：US17843938

申请日：2022-06-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRIYAL SHAH ,  MILIND S. BHAGAVAT ,  BRETT P. WILKERSON ,  LEI FU ,  RAHUL AGARWAL

IPC: H01L21/56 ,  H01L23/31

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

公开(公告)号：US20220208712A1

公开(公告)日：2022-06-30

申请号：US17134601

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL ,  RAJA SWAMINATHAN

IPC: H01L23/00 ,  H01L25/065

Abstract: A method of manufacturing a semiconductor device, including: bonding a first chip layer comprising a first semiconductor chip to a second chip layer comprising a second semiconductor chip to electrically couple an interconnect of the first semiconductor chip to a first interconnect of the second semiconductor chip; and bonding a third chip layer comprising a third semiconductor chip to the second chip layer to electrically couple an interconnect of the third semiconductor chip to a second interconnect of the second semiconductor chip.

公开(公告)号：US20210050223A1

公开(公告)日：2021-02-18

申请号：US17087388

申请日：2020-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL ,  MILIND S. BHAGAVAT ,  IVOR BARBER ,  VENKATACHALAM VALLIAPPAN ,  YUEN TING CHENG ,  GUAN SIN CHOK

IPC: H01L21/322 ,  H01L29/34 ,  H01L21/268

Abstract: Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.