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公开(公告)号：US20150095630A1
公开(公告)日：2015-04-02
申请号：US14083010
申请日：2013-11-18
Applicant: Apple Inc.
Inventor： Guy Cote , Joseph P. Bratt , Nitin Bhargava , Hao Chen , Joseph J. Cheng
IPC: G06F9/44
CPC classification number: G06F9/4401 , G06F3/0629 , G06F8/71 , G06F9/445
Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.
Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。
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公开(公告)号：US20130046938A1
公开(公告)日：2013-02-21
申请号：US13653109
申请日：2012-10-16
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Hao Chen
IPC: G06F12/00
CPC classification number: G06F9/5033 , G06F13/1668
Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
Abstract translation: 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。
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公开(公告)号：US12112663B2
公开(公告)日：2024-10-08
申请号：US18165648
申请日：2023-02-07
Applicant: Apple Inc.
Inventor： Juan He , Yi Huang , Jun Qi , ByoungSuk Kim , Hao Chen , Ping-Yen Chou , Yi-Pai Huang , Yue Ma , Sheng Zhang
IPC: G09G3/00
CPC classification number: G09G3/001 , G09G3/03 , G09G2320/02 , G09G2320/041 , G09G2320/0626
Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. The lenticular lenses may be configured to enable stereoscopic viewing of the display such that a viewer perceives three-dimensional images. To mitigate jaggedness in a curved edge of the active area, control circuitry may modify input pixel data for the display using dimming factors. Each brightness value of the pixel data may be multiplied by a corresponding dimming factor such that the curved edge has a smooth appearance. Each physical pixel in the display may have an associated perceived pixel that is based on an appearance of that physical pixel through the lenticular lens film. The perceived pixel may have a different footprint than its corresponding physical pixel. The dimming factors for boundary smoothing in the curved edges may be based on the perceived pixels.
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公开(公告)号：US20230326380A1
公开(公告)日：2023-10-12
申请号：US18165648
申请日：2023-02-07
Applicant: Apple Inc.
Inventor： Juan He , Yi Huang , Jun Qi , ByoungSuk Kim , Hao Chen , Ping-Yen Chou , Yi-Pai Huang , Yue Ma , Sheng Zhang
IPC: G09G3/00
CPC classification number: G09G3/001 , G09G3/03 , G09G2320/0626 , G09G2320/041 , G09G2320/02
Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. The lenticular lenses may be configured to enable stereoscopic viewing of the display such that a viewer perceives three-dimensional images. To mitigate jaggedness in a curved edge of the active area, control circuitry may modify input pixel data for the display using dimming factors. Each brightness value of the pixel data may be multiplied by a corresponding dimming factor such that the curved edge has a smooth appearance. Each physical pixel in the display may have an associated perceived pixel that is based on an appearance of that physical pixel through the lenticular lens film. The perceived pixel may have a different footprint than its corresponding physical pixel. The dimming factors for boundary smoothing in the curved edges may be based on the perceived pixels.
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公开(公告)号：US11619830B1
公开(公告)日：2023-04-04
申请号：US17705073
申请日：2022-03-25
Applicant: Apple Inc.
IPC: G02B30/33 , G02F1/137 , G02F1/13357 , G02F1/1335 , G02B30/27
Abstract: To enable a display to display different content to different viewers, a display may include a time-sequential directional backlight unit. The backlight unit may emit light in different directions in different configurations. In a first state, the backlight unit emits light at maximum brightness in a first direction. In a second state, the backlight unit emits light at maximum brightness in a second direction that is different than the first direction. The backlight unit may repeatedly and rapidly switch between the different states. The first direction may be towards a first viewer whereas the second direction may be towards a second, different viewer. Therefore, each viewer receives backlight in one of the configurations and does not receive backlight in the other configuration. In synchronization with the backlight unit, the liquid crystal display panel may repeatedly switch between displaying content for the first viewer and displaying content for the second viewer.
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Patent Agency Ranking
公开(公告)号：US10013046B2
公开(公告)日：2018-07-03
申请号：US15150109
申请日：2016-05-09
Applicant: Apple Inc.
Inventor： Peter F. Holland , Hao Chen , Sukalpa Biswas
CPC classification number: G06F1/3265 , G06F1/3206 , G06F1/3218 , G06F1/3225 , G06F1/3287 , G09G5/006 , G09G2330/021 , G09G2330/026 , G09G2340/06 , G09G2360/121
Abstract: Systems, apparatuses, and methods for improved power management techniques. An apparatus may include a display control unit, a communication fabric, a memory controller, a memory cache, and a memory. When the memory is power-gated, and the display control unit needs to fetch pixel data, the display control unit may send a wake-up signal to the memory before sending a wake-up signal to the communication fabric. The display control unit may then issue the pixel fetch request later. Additionally, if the display control unit determines that the pixel data has a high probability of being cached, then the display control unit may not send a wake-up signal to the memory, and the display control unit may issue the request earlier. More generally, the display control unit may send wake-up signals to multiple components in a manner which accounts for the wake-up latency of each component.
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公开(公告)号：US09135072B2
公开(公告)日：2015-09-15
申请号：US14017971
申请日：2013-09-04
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Hao Chen
CPC classification number: G06F9/5033 , G06F13/1668
Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
Abstract translation: 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。
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公开(公告)号：US20150070365A1
公开(公告)日：2015-03-12
申请号：US14019909
申请日：2013-09-06
Applicant: Apple Inc.
Inventor： Peter F. Holland , Albert C. Kuo , Hao Chen
CPC classification number: G06T1/20
Abstract: Embodiments of an apparatus and method are disclosed that may allow for arbitrating multiple read requests to fetch pixel data from a memory. The apparatus may include a first and a second processing pipeline, and a control unit. Each of the processing pipelines may be configured to generate a plurality of read requests to fetch a respective one of a plurality of portions of stored pixel data. The control unit may be configured to determine a priority for each read request dependent upon display coordinates of one or more pixels corresponding to each of the plurality of portions of stored pixel data, and determine an order for the plurality of read requests dependent upon the determined priority for each read request.
Abstract translation: 公开了可以允许仲裁多个读取请求以从存储器获取像素数据的装置和方法的实施例。 该装置可以包括第一和第二处理流水线以及控制单元。 每个处理流水线可以被配置为产生多个读取请求以获取存储的像素数据的多个部分中的相应一个。 控制单元可以被配置为根据与存储的像素数据的多个部分中的每一个相对应的一个或多个像素的显示坐标来确定每个读取请求的优先级，并且根据所确定的多个读取请求确定多个读取请求的顺序 每个读取请求的优先级。
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公开(公告)号：US08762653B2
公开(公告)日：2014-06-24
申请号：US14062302
申请日：2013-10-24
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
IPC: G06F12/00
CPC classification number: G06F13/1694 , G06F13/1684
Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
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公开(公告)号：US20250028365A1
公开(公告)日：2025-01-23
申请号：US18762491
申请日：2024-07-02
Applicant: Apple Inc.
Inventor： Wenyong Zhu , Sijun Niu , Wei Lv , Hao Chen , Ken Hsuan Liao , Tyler R Kakuda , Ying-Chih Wang
IPC: G06F1/16
Abstract: An electronic device may have a hinge that allows the device to be flexed about a bend axis. A display may span the bend axis. The device may have a stainless steel and/or carbon fiber reinforced polymer layer with slots. The slots may overlap the bend axis. The slots may have at least one property that varies in a non-linear manner as a function of position on the layer. The device may include an adhesive layer with a cutout that overlaps the slots. An interface that defines the cutout may have a plurality of recesses with varying depths. A flexible printed circuit may be attached to an edge of the display panel. The display cover layer may overlap a bonding region between the flexible printed circuit and the edge of the display panel. A UV-curable gap filler may be interposed between the flexible printed circuit and the display cover layer.
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