公开(公告)号：US10955893B2

公开(公告)日：2021-03-23

申请号：US16159821

申请日：2018-10-15

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32 ,  G06F1/3209 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US09419589B2

公开(公告)日：2016-08-16

申请号：US13968940

申请日：2013-08-16

Applicant: Apple Inc.

Inventor： Rohit Kumar

IPC: H03K3/012 ,  G06F1/10

CPC classification number: H03K3/012 ,  G06F1/10

Abstract: A clock distribution network having a separate power supply for top levels thereof is disclosed. In one embodiment, an integrated circuit includes a clock distribution network configured to distribute a clock signal to each of a number of clock consumers. The clock distribution network is arranged in a hierarchy of levels, with each of the levels including at least one buffer, and with the upper levels being closer to a source of the clock signal and the lower levels being closer to the clock consumers. The buffers of the upper levels are coupled to receive power from a first power source, via a first power grid. The buffers of the lower levels are coupled to receive power from a second power source, separate from the first, via a second power grid.

Abstract translation: 公开了一种具有用于其顶层的单独电源的时钟分配网络。 在一个实施例中，集成电路包括被配置为将时钟信号分配给多个时钟消费者中的每一个的时钟分配网络。 时钟分配网络被布置在层级中，其中每个级别包括至少一个缓冲器，并且上层级更靠近时钟信号源，而较低层级更接近时钟消费者。 上层的缓冲器被耦合以经由第一电网从第一电源接收电力。 较低级别的缓冲器被耦合以经由第二电力网从与第一电源分开的第二电源接收电力。

公开(公告)号：US20150198992A1

公开(公告)日：2015-07-16

申请号：US14157171

申请日：2014-01-16

Applicant: Apple Inc.

Inventor： Rohit Kumar ,  Suresh Periyacheri

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3293 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/152 ,  Y02D10/22

Abstract: An apparatus is disclosed for managing operational modes of a processor. The apparatus may include the processor which may include a coprocessor, an instruction queue, and a monitoring circuit for detecting instructions for the coprocessor in the instruction queue. The monitoring circuit may detect when the instruction queue holds no instructions for the coprocessor. If the instruction queue holds no instructions for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor consumes less power. The monitoring circuit may detect an instruction for the coprocessor in the instruction queue. In response to the instruction for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor may execute the instruction.

Abstract translation: 公开了一种用于管理处理器的操作模式的装置。 该装置可以包括可以包括协处理器，指令队列和用于检测指令队列中的协处理器的指令的监视电路的处理器。 监视电路可以检测指令队列何时不保存协处理器的指令。 如果指令队列不保存协处理器的指令，协处理器可以被置于协处理器消耗更少功率的模式中。 监视电路可以检测指令队列中协处理器的指令。 响应于协处理器的指令，协处理器可以被置于协处理器可以执行指令的模式中。

公开(公告)号：US20150048873A1

公开(公告)日：2015-02-19

申请号：US13968940

申请日：2013-08-16

Applicant: Apple Inc.

Inventor： Rohit Kumar

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G06F1/10

Abstract: A clock distribution network having a separate power supply for top levels thereof is disclosed. In one embodiment, an integrated circuit includes a clock distribution network configured to distribute a clock signal to each of a number of clock consumers. The clock distribution network is arranged in a hierarchy of levels, with each of the levels including at least one buffer, and with the upper levels being closer to a source of the clock signal and the lower levels being closer to the clock consumers. The buffers of the upper levels are coupled to receive power from a first power source, via a first power grid. The buffers of the lower levels are coupled to receive power from a second power source, separate from the first, via a second power grid.

Abstract translation: 公开了一种具有用于其顶层的单独电源的时钟分配网络。 在一个实施例中，集成电路包括被配置为将时钟信号分配给多个时钟消费者中的每一个的时钟分配网络。 时钟分配网络被布置在层级中，其中每个级别包括至少一个缓冲器，并且上层级更靠近时钟信号源，而较低层级更接近时钟消费者。 上层的缓冲器被耦合以经由第一电网从第一电源接收电力。 较低级别的缓冲器被耦合以经由第二电力网从与第一电源分开的第二电源接收电力。

公开(公告)号：US20140317425A1

公开(公告)日：2014-10-23

申请号：US13864723

申请日：2013-04-17

Applicant: APPLE INC.

Inventor： Wei-Han Lien ,  Gerard R. Williams, III ,  Rohit Kumar ,  Sandeep Gupta ,  Suresh Periyacheri ,  Shih-Chieh R. Wen

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

Abstract translation: 公开了一种用于执行多处理器系统的指令调节的装置。 该装置可以包括功率估计电路，表，比较器和有限状态机。 功率估计电路可以被配置为接收关于发给第一处理器和第二处理器的高功率指令的信息，并且根据所接收的信息生成功率估计。 该表可以被配置为存储一个或多个预定功率阈值，并且比较器可以被配置为将功率估计与预定功率阈值中的至少一个进行比较。 有限状态机可以被配置为根据比较的结果来调节第一和第二处理器的节气门位置。