公开(公告)号：US09171634B2

公开(公告)日：2015-10-27

申请号：US13827815

申请日：2013-03-14

Applicant: ARM LIMITED

Inventor： Bo Zheng ,  Gus Yeung ,  Fakhruddin ali Bohra

IPC: G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.

Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列具有主动操作模式，其中可以对该列组内的激活的存储器单元执行读取操作，以及读操作不可执行的非活动操作模式。 对于每个列组，预充电电路用于在读取操作之前将相关联的读取位线预充电到第一电压电平。 每个存储单元包括连接在相关读取位线和与包含该存储器单元的列组相关联的参考线之间的耦合电路。

公开(公告)号：US08963609B2

公开(公告)日：2015-02-24

申请号：US13782120

申请日：2013-03-01

Applicant: ARM Limited

Inventor： Gus Yeung ,  Srinivasan Srinath ,  Fakhruddin Ali Bohra

IPC: H03L5/00

CPC classification number: H03K19/0185

Abstract: An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains. The second combinatorial circuit portion has an output node whose voltage level identifies a value of the output signal and includes feedback circuitry which applies a level shifting function to an intermediate signal generated by the first combinatorial circuit portion. A contention mitigation circuitry reduces a voltage drop across at least one component within the feedback circuitry in situations when the combinatorial circuitry's performance of the combinatorial operation causes the combinatorial circuitry to switch the voltage on the output node, the contention mitigation circuitry thereby assists the combinatorial circuitry in the output node voltage switching.

Abstract translation: 集成电平移位组合电路在第一电压域中接收多个输入信号，并执行组合操作以在第二电压域中产生输出信号。 电路包括组合电路，其包括在相应的第一和第二电压域中操作的第一组合电路部分和第二组合电路部分。 第二组合电路部分具有输出节点，其电压电平标识输出信号的值，并且包括对由第一组合电路部分产生的中间信号施加电平移位功能的反馈电路。 在组合电路的组合操作的性能导致组合电路切换输出节点上的电压的情况下，争用减轻电路减少了反馈电路内的至少一个组件上的电压降，争用缓解电路因此有助于组合电路 在输出节点电压切换。

公开(公告)号：US11288432B2

公开(公告)日：2022-03-29

申请号：US17062567

申请日：2020-10-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Gus Yeung ,  Marlin Wayne Frederick, Jr. ,  Sriram Thyagarajan

IPC: G06F30/39 ,  G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.

公开(公告)号：US10796053B2

公开(公告)日：2020-10-06

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, Jr. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50 ,  G06F30/39 ,  G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20200014373A1

公开(公告)日：2020-01-09

申请号：US16026946

申请日：2018-07-03

Applicant: Arm Limited

Inventor： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC: H03K5/06 ,  G06F12/0804

Abstract: Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

公开(公告)号：US09600179B2

公开(公告)日：2017-03-21

申请号：US14446668

申请日：2014-07-30

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Michael Alan Filippo ,  Gus Yeung ,  Andy Wangkun Chen ,  Sriram Thyagarajan

IPC: G11C8/08 ,  G06F3/06 ,  G06F1/32 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22

CPC classification number: G06F3/06 ,  G06F1/3275 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.

公开(公告)号：US09542986B2

公开(公告)日：2017-01-10

申请号：US14849902

申请日：2015-09-10

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Gus Yeung ,  Yew Keong Chong

IPC: G11C8/18 ,  G11C8/06

CPC classification number: G11C8/18 ,  G11C5/141 ,  G11C8/06

Abstract: Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.

Abstract translation: 本文所描述的各种实现涉及用于实现低功率输入门控的集成电路。 在一个实现中，集成电路可以包括芯片使能装置，其被配置为接收和使用时钟输入信号，以基于芯片使能信号切换存储器的控制输入。 集成电路可以包括被配置为锁存存储器的控制输入的锁存装置。 集成电路可以包括耦合在芯片使能装置和锁存装置之间的锁存使能装置。 锁存使能装置可以被配置为从芯片使能装置接收时钟输入信号，并且使用时钟输入信号基于锁存使能信号来对锁存器件进行门控，以便有选择地将时钟输入信号切换到控制输入 的记忆。

公开(公告)号：US20160034403A1

公开(公告)日：2016-02-04

申请号：US14446668

申请日：2014-07-30

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Michael Alan Filippo ,  Gus Yeung ,  Andy Wangkun Chen ,  Sriram Thyagarajan

IPC: G06F12/08

CPC classification number: G06F3/06 ,  G06F1/3275 ,  G11C7/00 ,  G11C7/08 ,  G11C7/22 ,  G11C8/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory device and a method of operating the memory device are provided. The memory device comprises a plurality of storage units and access control circuitry. The access control is configured to receive an access request and in response to the access request to initiate an access procedure in each of the plurality of storage units. The access control circuitry is configured to receive an access kill signal after the access procedure has been initiated and, in response to the access kill signal, to initiate an access suppression to suppress the access procedure in at least one of the plurality of storage units. Hence, by initiating the access procedures in all storage units in response to the access request, e.g. without waiting for a further indication of a specific storage unit in which to carry out the access procedure, the overall access time for the memory device kept low, but by enabling at least one of the access procedures later to be suppressed in response to the access kill signal dynamic power consumption of the memory device can be reduced.

Abstract translation: 提供了存储器件和操作存储器件的方法。 存储器件包括多个存储单元和访问控制电路。 访问控制被配置为接收访问请求并且响应于访问请求以在多个存储单元中的每一个中发起访问过程。 所述访问控制电路被配置为在所述访问过程已经被启动之后接收访问终止信号，并且响应于所述访问禁止信号来启动访问抑制以抑制所述多个存储单元中的至少一个中的访问过程。 因此，通过响应于访问请求在所有存储单元中启动访问过程，例如， 在不等待对其进行访问过程的特定存储单元的进一步指示的情况下，存储器件的总访问时间保持为低，但是通过使访问过程中的至少一个随后能够被响应于访问被抑制 杀死信号动态功耗的存储器件可以减少。

公开(公告)号：US09069652B2

公开(公告)日：2015-06-30

申请号：US13782077

申请日：2013-03-01

Applicant: ARM LIMITED

Inventor： Gus Yeung ,  Bo Zheng ,  Frank Guo

IPC: G11C7/00 ,  G06F12/00 ,  G11C5/14 ,  G11C11/417 ,  G11C7/10

CPC classification number: G06F12/00 ,  G11C5/147 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1084 ,  G11C7/1087 ,  G11C11/417

Abstract: An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.

Abstract translation: 集成电平移位锁存电路接收第一电压域中的输入信号并在第二电压域中产生输出信号。 数据保持电路在透明阶段工作，其中数据值经受电平移位功能，并根据输入信号写入数据保持电路。 控制电路控制数据保持电路在时钟信号的第一阶段期间在透明阶段中工作，并且在时钟信号的第二阶段期间操作在锁存阶段。 写入电路将数据值写入数据保持电路。 竞争缓解电路在透明阶段期间减少数据保持电路内的至少一个组件的压降。

公开(公告)号：US20150049568A1

公开(公告)日：2015-02-19

申请号：US13967908

申请日：2013-08-15

Applicant: ARM Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Wang-Kun Chen ,  Gus Yeung

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C7/10 ,  G11C8/06

Abstract: A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.

Abstract translation: 存储器件包括排列成多行比特单元和多列比特单元的位单元阵列，并且具有多个字线和多个读出通道。 控制单元被配置为控制对位单元阵列的访问，其中响应于指定存储器地址的存储器访问请求，控制单元被配置为激活所选择的字线并激活多个读出通道，并且访问行 所述阵列中的位单元存储数据字并由存储器地址寻址。 数据字由每行位单元中的多个位单元给出的多个数据位组成。 所述控制单元还被配置为响应于屏蔽信号，并且当接收到所述存储器访问请求时屏蔽信号被断言时，所述控制单元被配置为仅激活所选字线的一部分和所述多个 读出通道，使得仅访问数据字的一部分。