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公开(公告)号：US20190042253A1
公开(公告)日：2019-02-07
申请号：US15665781
申请日：2017-08-01
Applicant: ARM Limited
Inventor： Mbou EYOLE , Jesse Garrett BEU , Alejandro Martinez VICENTE , Timothy HAYES
IPC: G06F9/30
Abstract: An apparatus and method of operating the apparatus are provided for performing a count operation. Instruction decoder circuitry is responsive to a count instruction specifying an input data item to generate control signals to control the data processing circuitry to perform a count operation. The count operation determines a count value indicative of a number of input elements of a subset of elements in the specified input data item which have a value which matches a reference value in a reference element in a reference data item. A plurality of count operations may be performed to determine a count data item corresponding to the input data item. A register scatter storage instruction, a gather index generation instruction, and respective apparatuses responsive to them, as well as simulator implementations, are also provided.
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公开(公告)号：US20190042190A1
公开(公告)日：2019-02-07
申请号：US15665715
申请日：2017-08-01
Applicant: ARM Limited
Inventor： Alejandro Martinez VICENTE , Jesse Garrett BEU , Mbou EYOLE , Timothy HAYES
Abstract: An apparatus and a method of operating the apparatus are provided for performing a comparison operation to match a given sequence of values within an input vector. Instruction decoder circuitry is responsive to a string match instruction specifying a segment of an input vector to generate control signals to control the data processing circuitry to perform a comparison operation. The comparison operation determines a comparison value indicative of whether each input element of a required set of consecutive input elements of the segment has a value which matches a respective value in consecutive reference elements of the reference data item. A plurality of comparison operations may be performed to determine a match vector corresponding to the segment of the input vector to indicate the start position of the substring in the input vector. A string match instruction, as well as simulator virtual machine implementations, are also provided.
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公开(公告)号：US20170031682A1
公开(公告)日：2017-02-02
申请号：US14814582
申请日：2015-07-31
Applicant: ARM LIMITED
Inventor： Jacob EAPEN , Mbou EYOLE , Simon HOSIE
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032
Abstract: An apparatus comprises processing circuitry to generate a result vector including at least one N-bit data element in response to an element size increasing instruction identifying at least a first input vector including M-bit data elements, where N>M. First and second forms of the element size increasing instruction are provided for generating the result vector using first and second subsets of data elements of the first input vector respectively. Positions of the first and second subsets of data elements in the first input vector are interleaved.
Abstract translation: 一种装置包括处理电路，以响应于识别包括M位数据元素的至少第一输入向量的元素大小增加指令来生成包括至少一个N位数据元素的结果向量，其中N> M。 提供元素大小增加指令的第一和第二形式，用于分别使用第一输入向量的数据元素的第一和第二子集来生成结果向量。 数据元素的第一和第二子集在第一输入向量中的位置被交织。
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公开(公告)号：US20240184849A1
公开(公告)日：2024-06-06
申请号：US18074636
申请日：2022-12-05
Applicant: Arm Limited
Inventor： Emre ÖZER , Sahan Sajeewa Hiniduma Udugama GAMAGE , Mbou EYOLE , Fernando Garcia REDONDO , Jedrzej KUFEL , John Philip BIGGS
Abstract: Apparatuses, corresponding methods, and instructions for data processing for the generation of an approximate quantile are provided. A sequence of data values is received, wherein the data values span a range of values and in a plurality of counters each counter is configured to have a correspondence to a subrange within the range of values. For each data value received a corresponding counter of the plurality of counters is determined and an update is applied to the corresponding counter of the plurality of counters. Approximate quantile determination is performed to generate at least one approximate quantile value for the sequence of data values received in dependence on respective counts of the plurality of counters.
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公开(公告)号：US20240086196A1
公开(公告)日：2024-03-14
申请号：US17941387
申请日：2022-09-09
Applicant: Arm Limited
Inventor： Matthew James WALKER , Mbou EYOLE , Giacomo GABRIELLI , Balaji VENU
CPC classification number: G06F9/30123 , G06F9/4881
Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.
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Patent Agency Ranking
公开(公告)号：US20230185651A1
公开(公告)日：2023-06-15
申请号：US17547963
申请日：2021-12-10
Applicant: Arm Limited
Inventor： Emre OZER , Mbou EYOLE , Jedrzej KUFEL , John Philip BIGGS
CPC classification number: G06F11/0787 , G06F13/24 , G06F30/20
Abstract: Methods of performing post-manufacturing adaptation of a data processing apparatus manufactured in accordance with a processor design and corresponding data processing apparatus configurations are provided. Post-manufacturing testing of the data processing apparatus determines any dysfunctional instructions by comparison between component usage profiles for each instruction and a component fault-detection procedure applied to the data processing apparatus. The data processing apparatus can be determined nevertheless to be operationally viable when any dysfunctional instructions can be substituted for by emulation using other functional instructions. The data processing apparatus can be provided with dysfunctional instruction handling circuitry configured to identify occurrence of a program instruction instance of a dysfunctional instruction and to invoke an interrupt handling routine associated with the dysfunctional instruction to emulate the instance of a dysfunctional instruction.
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公开(公告)号：US20230064455A1
公开(公告)日：2023-03-02
申请号：US17754739
申请日：2020-09-28
Applicant: Arm Limited
Inventor： Mbou EYOLE , Michiel Willem VAN TOL
Abstract: A data processing apparatus and method of operating such is disclosed. Issue circuitry buffers operations prior to execution until operands are available in a set of registers. A first and a second load operation are identified in the issue circuitry, when both are dependent on a common operand, and when the common operand is available in the set of registers. Load circuitry has a first address generation unit to generate a first address for the first load operation and a second address generation unit to generate a second address for the second load operation. An address comparison unit compares the first address and the second address. The load circuitry is arranged to cause a merged lookup to be performed in local temporary storage, when the address comparison unit determines that the first and the second address differ by less than a predetermined address range characteristic of the local temporary storage.
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公开(公告)号：US20220391214A1
公开(公告)日：2022-12-08
申请号：US17755130
申请日：2020-10-15
Applicant: Arm Limited
Inventor： Mbou EYOLE , Stefanos KAXIRAS
Abstract: An apparatus comprises first instruction execution circuitry, second instruction execution circuitry, and a decoupled access buffer. Instructions of an ordered sequence of instructions are issued to one of the first and second instruction execution circuitry for execution in dependence on whether the instruction has a first type label or a second type label. An instruction with the first type label is an access-related instruction which determines at least one characteristic of a load operation to retrieve a data value from a memory address. Instruction execution by the first instruction execution circuitry of instructions having the first type label is prioritised over instruction execution by the second instruction execution circuitry of instructions having the second type label. Data values retrieved from memory as a result of execution of the first type instructions are stored in the decoupled access buffer.
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公开(公告)号：US20220391101A1
公开(公告)日：2022-12-08
申请号：US17755133
申请日：2020-10-07
Applicant: ARM LIMITED
Inventor： Mbou EYOLE , Stefanos KAXIRAS
IPC: G06F3/06
Abstract: When load requests are generated to support data processing operations, the load requests are buffered in pending load buffer circuitry prior to being carried out. Coalescing circuitry determines for a first load request whether a set of one or more subsequent load requests buffered in the pending load buffer circuitry satisfies an address proximity condition. The address proximity condition is satisfied when all data items identified by the set of one or more subsequent load requests are comprised within a series of data items which will be retrieved from the memory system in response to the first load request. When the address proximity condition is satisfied, forwarding of the set of one or more subsequent load requests is suppressed.
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公开(公告)号：US20200319885A1
公开(公告)日：2020-10-08
申请号：US16650999
申请日：2018-11-15
Applicant: Arm Limited
Inventor： Mbou EYOLE , Nigel John STEPHENS , Neil BURGESS , Grigorios MAGKLIS
Abstract: Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.
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