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    Data driven scheduler on multiple computing cores
    21.
    发明授权
    Data driven scheduler on multiple computing cores 有权

    公开(公告)号：US10649810B2

    公开(公告)日：2020-05-12

    申请号：US14981257

    申请日：2015-12-28

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Jimshed Mirza ,  YunPeng Zhu

    IPC: G06F9/50

    Abstract: Methods, devices, and systems for data driven scheduling of a plurality of computing cores of a processor. A plurality of threads may be executed on the plurality of computing cores, according to a default schedule. The plurality of threads may be analyzed, based on the execution, to determine correlations among the plurality of threads. A data driven schedule may be generated based on the correlations. The plurality of threads may be executed on the plurality of computing cores according to the data driven schedule.

    Selecting a default page size in a variable page size TLB
    23.
    发明授权
    Selecting a default page size in a variable page size TLB 有权

    公开(公告)号：US10241925B2

    公开(公告)日：2019-03-26

    申请号：US15433560

    申请日：2017-02-15

    Applicant: ATI Technologies ULC

    Inventor： Jimshed Mirza ,  Anthony Chan ,  Edwin Chi Yeung Pang

    IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009

    Abstract: Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed. In one embodiment, a system includes at least one processor, a memory subsystem, and a first TLB. The first TLB is configured to allocate a first entry for a first request responsive to detecting a miss for the first request in the first TLB. Prior to determining a page size targeted by the first request, the first TLB specifies, in the first entry, that the first request targets a page of a first page size. Responsive to determining that the first request actually targets a second page size, the first TLB reissues the first request with an indication that the first request targets the second page size. On the reissue, the first TLB allocates a second entry and specifies the second page size for the first request.

    FLEXIBLE SHADER EXPORT DESIGN IN MULTIPLE COMPUTING CORES
    25.
    发明申请
    FLEXIBLE SHADER EXPORT DESIGN IN MULTIPLE COMPUTING CORES 审中-公开

    公开(公告)号：US20180314528A1

    公开(公告)日：2018-11-01

    申请号：US15607118

    申请日：2017-05-26

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Yunpeng Zhu ,  Jimshed Mirza

    IPC: G06F9/38 ,  G06F9/48

    Abstract: Systems, apparatuses, and methods for generating flexibly addressed memory requests are disclosed. In one embodiment, a system includes a processor, control unit, and memory subsystem. The processor launches a plurality of threads on a plurality of compute units, wherein each thread generates memory requests without specifying target memory addresses. The threads executing on the plurality of compute units convey a plurality of memory requests to the control unit. The control unit generates target memory addresses for the plurality of received memory requests. In one embodiment, the memory requests are write requests, and the control unit interleaves write requests from the plurality of threads into a single output buffer stored in the memory subsystem. The control unit can be located in a cache, in a memory controller, or in another location within the system.

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