公开(公告)号：US20180183455A1

公开(公告)日：2018-06-28

申请号：US15849220

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link ,  Jian Li

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/462 ,  H03M1/0863 ,  H03M1/1019 ,  H03M1/1061 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/129 ,  H03M1/466 ,  H03M1/468

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a successive approximation register (SAR) unit including one or more capacitive networks. The capacitive networks take a sample of an analog signal. The SAR also includes a comparator to approximate digital values based on the analog signal sample via successive comparison. The ADC includes a preamplifier coupled to the SAR unit. The preamplifier amplifies the analog signal for application to the capacitive networks for sampling. The ADC also includes a rough buffer coupled to the SAR unit. The rough buffer pre-charges the capacitive networks of the SAR unit prior to application of the analog signal from the preamplifier.

公开(公告)号：US20190179355A1

公开(公告)日：2019-06-13

申请号：US16159491

申请日：2018-10-12

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Wai Lee

IPC: G05F3/26

Abstract: A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.

公开(公告)号：US10243579B2

公开(公告)日：2019-03-26

申请号：US15832503

申请日：2017-12-05

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link

IPC: H03M1/00 ,  H03M1/46 ,  H03M1/06 ,  H03M1/80 ,  H03M1/16 ,  H03M1/14 ,  H03M1/12 ,  H03M1/18

Abstract: The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

公开(公告)号：US20180337636A1

公开(公告)日：2018-11-22

申请号：US15984250

申请日：2018-05-18

Applicant: Avnera Corporation

Inventor： Gilbert C. Martinez ,  Amit Kumar ,  Ali Hadiashar ,  Mark Gehring ,  Wai Lee

IPC: H03F1/02 ,  H03F3/183 ,  H03M1/00 ,  H03M3/00 ,  H03G3/30

Abstract: An audio system can include an amplifier having two parallel drivers, one having common source transistors and one having common drain transistors, also called source following. At low signals, the source followers dominate the open-loop gain signal path, while large signals cause the common source transistors to be dominant. At low signal amplitudes, the common source transistor gain is reduced and the common drain transistors provide the load current. At a pre-determined level of signal amplitude, the common source transistors take over and provide the current load. A calibration system for a DAC is also provided. The calibration system measures individual cell performance in the DAC, then stores its digital equivalent in a coefficient storage. Then, a quantizer can refer to the stored coefficients when selecting the appropriate final quantized digital value.

公开(公告)号：US20180183456A1

公开(公告)日：2018-06-28

申请号：US15849227

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link ,  Jianping Wen

IPC: H03M1/46 ,  H03M1/44

CPC classification number: H03M1/462 ,  H03M1/0626 ,  H03M1/08 ,  H03M1/442 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

公开(公告)号：US20180181157A1

公开(公告)日：2018-06-28

申请号：US15852757

申请日：2017-12-22

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Wai Lee

IPC: G05F3/26

CPC classification number: G05F3/262 ,  G05F1/10 ,  G05F3/02 ,  G05F3/26

Abstract: A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.