公开(公告)号：US20100072557A1

公开(公告)日：2010-03-25

申请号：US12628910

申请日：2009-12-01

Applicant: Larson Lindholm ,  Aaron R. Wilson ,  David K. Hwang

Inventor： Larson Lindholm ,  Aaron R. Wilson ,  David K. Hwang

IPC: H01L27/092

CPC classification number: H01L27/10891 ,  H01L21/31116 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.

Abstract translation: 一些实施方案包括使用包含C 4 F 6和C 4 F 3的蚀刻剂将多种材料凹入共同深度的方法。 凹陷的材料可以在隔离区域内，并且凹陷可以用于形成用于接收基准线的沟槽。 一些实施例包括具有由电绝缘材料横向包围的半导体材料岛的结构。 两种栅极延伸穿过绝缘材料和半导体材料岛。 电绝缘材料中的一种比另一种更凹陷。

公开(公告)号：US20090026530A1

公开(公告)日：2009-01-29

申请号：US11778938

申请日：2007-07-17

Applicant: Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。 在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在所述一对STI结构之间的衬底的一部分中限定凹陷，以及凹陷 STI结构使得所得到的双翅片结构从基板的有效表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

公开(公告)号：US06689282B2

公开(公告)日：2004-02-10

申请号：US10198873

申请日：2002-07-19

Applicant: Aaron R. Wilson

Inventor： Aaron R. Wilson

IPC: H01J904

CPC classification number: H01J9/025

Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.

Abstract translation: 公开了一种形成用于场致发射阵列的发射极尖端的方法。 尖端通过利用在干蚀刻锐化步骤期间形成的聚合物残余物形成，以将掩模帽保持在发射器尖端上的适当位置。 当尖端被过蚀刻时，残余聚合物继续支撑掩模帽，使得尖端能够被锐利地蚀刻而不会损失它们的形状和锐度。 干蚀刻使用由氟和氯气组成的蚀刻剂。 通过在去离子水或缓冲氧化物蚀刻的洗涤中洗涤晶片，蚀刻后容易除去掩模盖和残余聚合物。

公开(公告)号：US06679998B2

公开(公告)日：2004-01-20

申请号：US10227262

申请日：2002-08-23

Applicant: Eric J. Knappenberger ,  Aaron R. Wilson

Inventor： Eric J. Knappenberger ,  Aaron R. Wilson

IPC: B44C122

CPC classification number: H01J9/025

Abstract: A method of forming a pattern in a layer of material on a substrate, comprising providing a plurality of spheres, covering the layer on the substrate with the plurality of spheres to form a mask, reducing the diameter of at least one sphere of the plurality of spheres, etching the layer on the substrate using at least one sphere having a reduced diameter as a mask, and etching the substrate.

Abstract translation: 一种在衬底上的材料层中形成图案的方法，包括提供多个球体，用所述多个球体覆盖所述衬底上的所述层以形成掩模，从而减小所述多个球体中的至少一个球体的直径 使用至少一个直径减小的球体作为掩模蚀刻在基板上的层，并蚀刻该基板。

公开(公告)号：US06660173B2

公开(公告)日：2003-12-09

申请号：US10153195

申请日：2002-05-22

Applicant: Aaron R. Wilson

Inventor： Aaron R. Wilson

IPC: H01J904

CPC classification number: H01J9/025

Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.

公开(公告)号：US06649469B1

公开(公告)日：2003-11-18

申请号：US10269302

申请日：2002-10-11

Applicant: Aaron R. Wilson

Inventor： Aaron R. Wilson

IPC: H01L218242

CPC classification number: H01L28/91 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/10852

Abstract: A carbon containing masking layer is patterned to include a plurality of container openings therein having minimum feature dimensions of less than or equal to 0.20 micron. The container openings respectively have at least three peripheral corner areas which are each rounded. The container forming layer is plasma etched through the masking layer openings. In one implementation, such plasma etching uses conditions effective to both a) etch the masking layer to modify shape of the masking layer openings by at least reducing degree of roundness of the at least three corners in the masking layer, and b) form container openings in the container forming layer of the modified shapes. Capacitors comprising container shapes are formed using the container openings in the container forming layer. Other implementations and aspects are disclosed.

Abstract translation: 含碳掩蔽层被图案化以包括其中具有小于或等于0.20微米的最小特征尺寸的多个容器开口。 容器开口分别具有至少三个周边角区域，每个周边角部分均为圆形。 容器形成层通过掩模层开口进行等离子体蚀刻。 在一个实施方案中，这种等离子体蚀刻使用有效的条件，a）蚀刻掩模层以通过至少减少掩模层中的至少三个角的圆度来修改掩模层开口的形状，以及b）形成容器开口 在容器形成层中形成改性的形状。 使用容器形成层中的容器开口形成包含容器形状的电容器。 公开了其他实现和方面。

公开(公告)号：US08497530B2

公开(公告)日：2013-07-30

申请号：US13424234

申请日：2012-03-19

Applicant: Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: Fin-FET（鳍场效应晶体管）器件和制造方法被公开。 鳍式FET器件包括可在源极区域和漏极区域之间形成沟道区域的双鳍结构。 在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在一对STI结构之间限定衬底的一部分中的凹部，以及凹陷 所述一对STI结构使得所得到的双翅片结构从所述基板的有效表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

公开(公告)号：US08419958B2

公开(公告)日：2013-04-16

申请号：US12777420

申请日：2010-05-11

Applicant: Aaron R. Wilson

Inventor： Aaron R. Wilson

IPC: G01R31/00 ,  C23F1/00

CPC classification number: H01L21/3065 ,  H01J37/32706 ,  H01L21/6833 ,  H02N13/00

Abstract: Apparatus, systems and methods for plasma etching substrates are provided that achieve dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features. Charge build-up on a substrate being etched by plasma etching can be dissipated by a method for etching a substrate, the method comprising: providing a plasma processing chamber comprising a chamber enclosure and a substrate support adapted to support a substrate within the chamber enclosure; supporting a substrate on the substrate support; forming a plasma within the chamber enclosure such that a surface of the substrate is in contact with the plasma; etching the substrate by generating a negative bias on the substrate surface relative to the plasma; and intermittently changing the bias on the substrate surface to positive relative to the plasma. The present method can be integrated into known plasma processing systems.

Abstract translation: 提供了用于等离子体蚀刻衬底的装置，系统和方法，其实现在等离子体蚀刻的衬底上的电荷积聚的消散，以避免在高纵横比内容和类似特征中的开槽或扭曲。 通过等离子体蚀刻蚀刻的衬底上的电荷积聚可以通过用于蚀刻衬底的方法来消散，该方法包括：提供等离子体处理室，其包括适于支撑腔室外壳内的衬底的腔室封壳和衬底支撑件; 支撑衬底支撑上的衬底; 在所述室外壳内形成等离子体，使得所述基板的表面与所述等离子体接触; 通过在衬底表面上相对于等离子体产生负偏压来蚀刻衬底; 并且间歇性地将衬底表面上的偏压相对于等离子体改变为正。 本方法可以集成到已知的等离子体处理系统中。

公开(公告)号：US20120175748A1

公开(公告)日：2012-07-12

申请号：US13424234

申请日：2012-03-19

Applicant: Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。 在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在所述一对STI结构之间的衬底的一部分中限定凹陷，以及凹陷 所述一对STI结构使得所得到的双翅片结构从所述基板的有源表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

公开(公告)号：US20100327369A1

公开(公告)日：2010-12-30

申请号：US12875828

申请日：2010-09-03

Applicant: Larson Lindholm ,  Aaron R. Wilson ,  David K. Hwang

Inventor： Larson Lindholm ,  Aaron R. Wilson ,  David K. Hwang

IPC: H01L27/092

CPC classification number: H01L27/10891 ,  H01L21/31116 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.