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公开(公告)号：US06604162B1
公开(公告)日：2003-08-05
申请号：US09606837
申请日：2000-06-28
IPC分类号： G06F1342
CPC分类号： G06F12/0831 , G06F13/4243
摘要： A method and apparatus for reducing snoop stall on an external bus. One method of the present invention comprises retrieving an address and a transaction attribute for a bus transaction during a first of a plurality of request phase packets of the bus transaction. Then it is determined whether the bus transaction is a snoopable memory transaction or not. If the bus transaction is a snoopable memory transaction, a snoop probe is dispatched during the first request phase packet of the transaction. Snooping devices are allowed additional bus clocks to respond to the snoop probe, thereby reducing the number of snoop stalls required to be inserted during the bus transaction.
摘要翻译： 一种用于减少外部总线上的窥探失速的方法和装置。 本发明的一种方法包括在总线事务的多个请求阶段分组的第一个期间检索总线事务的地址和事务属性。 然后确定总线事务是否是可窥探的存储器事务。 如果总线事务是可窥探的内存事务，则在事务的第一请求阶段数据包期间调度侦听器探测。 侦听设备允许额外的总线时钟响应窥探探针，从而减少在总线事务期间插入所需的监听档位数。
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公开(公告)号：US06507219B2
公开(公告)日：2003-01-14
申请号：US09962716
申请日：2001-09-21
申请人： Sanjay Dabral , Ming Zeng , Subramaniam Maiyuran
发明人： Sanjay Dabral , Ming Zeng , Subramaniam Maiyuran
IPC分类号： H03K19094
CPC分类号： G11C7/106 , G06F13/4077 , G11C7/1051 , G11C7/1078 , G11C7/1087 , H03K19/01855 , Y02D10/14 , Y02D10/151
摘要： A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.
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公开(公告)号：US06356270B2
公开(公告)日：2002-03-12
申请号：US09053231
申请日：1998-03-31
IPC分类号： G06T160
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/0875
摘要： The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.
摘要翻译： 本发明公开了一种用于对分散位置的非时间存储序列的写合成缓冲器有效利用的方法和装置方法。 该方法包括：将非时间存储序列转换为存储到中间缓冲器; 并将商店分组到中间缓冲器到连续的非时间商店。 连续的非时间存储对应于写合成缓冲器中的相邻存储器位置。
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公开(公告)号：US09098268B2
公开(公告)日：2015-08-04
申请号：US13619832
申请日：2012-09-14
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
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公开(公告)号：US08959314B2
公开(公告)日：2015-02-17
申请号：US13942660
申请日：2013-07-15
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
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26.发明申请MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM 审中-公开MFENCE和LFENCE微结构实现方法与系统公开(公告)号：US20130205117A1
公开(公告)日：2013-08-08
申请号：US13838229
申请日：2013-03-15
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译： 一种用于防止内存访问的系统和方法。 存储器负载可以围栏，或者所有内存访问都可以被围起来。 系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。 存储器排序单元内的缓冲器被分配给该指令。 比栅栏指令更新的访问指令被停止。 旧的访问指令已逐渐退出。 当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。
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公开(公告)号：US08448010B2
公开(公告)日：2013-05-21
申请号：US12570137
申请日：2009-09-30
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066
摘要： The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.
摘要翻译： 可以通过在时钟的高阶段和低阶段之间传送信息来增加可在处理单元和存储器之间传送的数据量。 作为一个例子，在使用通用寄存器文件作为存储器和数学框作为处理单元的图形处理器中，可以通过在时钟的高阶段和低阶段之间传送数据来增加可以传送的数据量 。
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28.发明申请公开(公告)号：US20120191951A1
公开(公告)日：2012-07-26
申请号：US13440096
申请日：2012-04-05
IPC分类号： G06F9/312
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译： 一种用于防止内存访问的系统和方法。 存储器负载可以围栏，或者所有内存访问都可以被围起来。 系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。 存储器排序单元内的缓冲器被分配给该指令。 比栅栏指令更新的访问指令被停止。 旧的访问指令已逐渐退出。 当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。
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公开(公告)号：US07457917B2
公开(公告)日：2008-11-25
申请号：US11027413
申请日：2004-12-29
CPC分类号： G06F12/0875 , G06F9/3802 , G06F9/3804 , G06F12/0846 , G06F12/0864 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括高速缓冲存储器，其可以是具有多个存储体的顺序高速缓存。 每个存储体包括数据阵列，耦合到数据阵列的解码器以选择一组数据阵列，以及读出放大器。 只有要访问的存储体可以被供电，并且在一些实施例中，可以使用早期路径信息来维持处于功率降低状态的剩余存储体。 在一些实施例中，可以使用时钟选通来维持处于功率降低状态的高速缓冲存储器的各种组件。 描述和要求保护其他实施例。
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公开(公告)号：US07124277B2
公开(公告)日：2006-10-17
申请号：US10646033
申请日：2003-08-22
CPC分类号： G06F9/3802 , G06F9/3808
摘要： A method and apparatus for a trace end predictor for a trace cache is disclosed. In one embodiment, the trace end predictor may have one or more buffers to contain a head address for a subsequent trace. The head address may include the way number and set number of the next head, along with partial stew data to support additional execution predictors. The buffers may also include tag data of the current trace's tail address, and may additionally include control bits for determining whether to replace the buffer's contents with information from another trace's tail. Reading the next head address from the trace end predictor, as opposed to reading it from the trace cache array, may reduce certain execution time delays.
摘要翻译： 公开了一种用于跟踪高速缓存的跟踪结束预测器的方法和装置。 在一个实施例中，跟踪结束预测器可以具有一个或多个缓冲器以包含后续跟踪的头地址。 头部地址可以包括下一个头部的路径编号和编号，以及部分炖菜数据以支持附加的执行预测器。 缓冲器还可以包括当前迹线的尾部地址的标签数据，并且还可以包括用于确定是否用来自另一跟踪尾部的信息替换缓冲器内容的控制位。 从跟踪结束预测器读取下一个头地址，而不是从跟踪高速缓存阵列读取它，可能会减少某些执行时间延迟。
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