利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

27 条记录 (耗时 0.016 秒)

    Low cost and high speed 3 load printed wiring board bus topology
    5.
    发明授权
    Low cost and high speed 3 load printed wiring board bus topology 失效

    公开(公告)号：US06561410B2

    公开(公告)日：2003-05-13

    申请号：US10116503

    申请日：2002-04-03

    申请人： Sanjay Dabral ,  Ming Zeng

    发明人： Sanjay Dabral ,  Ming Zeng

    IPC分类号： B23K3102

    CPC分类号： H05K1/0246 ,  G06F13/4086 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49155

    摘要： A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.

    Low cost and high speed 3-load printed wiring board bus topology
    8.
    发明授权
    Low cost and high speed 3-load printed wiring board bus topology 有权
    低成本和高速3负载印刷线路板总线拓扑

    公开(公告)号：US06417462B1

    公开(公告)日：2002-07-09

    申请号：US09596613

    申请日：2000-06-19

    申请人： Sanjay Dabral ,  Ming Zeng

    发明人： Sanjay Dabral ,  Ming Zeng

    IPC分类号： H01R909

    CPC分类号： H05K1/0246 ,  G06F13/4086 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49155

    摘要： A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.

    摘要翻译： 公开了一种具有3负载拓扑结构的多层印刷电路板。 具有第一，第二和第三组端子的第一，第二和第三集成电路（IC）印刷电路板封装分别安装在板的相对侧上，使得第二组端子与第三组端子正对。 每个封装包含耦合到相应的一组端子的IC管芯。 第一封装中的IC管芯基本上与第二封装中包含的IC管芯相同，并且与第三封装件中包含的IC管芯不同。 为了改善将第一封装与第二和第三封装互连的金属线的扇出，将封装中的第一组，第二组和第三组端子中的每一个布置成大致U形。 每组终端具有由板中的金属线实现的并行总线的相同的一组信号分配。 3负载拓扑结构对于具有双处理器和桥接芯片组的个人计算机主板单元特别有用，产生具有显着更低数量金属层的母板，更快的总线和显着改善的噪声容限，所有这些都具有高密度IC封装 宽并行总线。

    Method and apparatus for generating a reference voltage signal derived from complementary signals
    9.
    发明授权
    Method and apparatus for generating a reference voltage signal derived from complementary signals 有权
    用于产生从互补信号导出的参考电压信号的方法和装置

    公开(公告)号：US06278312B1

    公开(公告)日：2001-08-21

    申请号：US09256843

    申请日：1999-02-24

    申请人： Sanjay Dabral ,  Ming Zeng

    发明人： Sanjay Dabral ,  Ming Zeng

    IPC分类号： H03L508

    CPC分类号： H04L25/062

    摘要： A driver circuit and a receiver circuit. The driver circuit is coupled to drive two complementary signals and the receiver is coupled to receive the two complementary signals. The receiver circuit generates a reference voltage from the two complementary signals.

    摘要翻译： 驱动电路和接收器电路。 驱动电路被耦合以驱动两个互补信号，并且接收器被耦合以接收两个互补信号。 接收器电路从两个互补信号产生参考电压。

    Testing for digital signaling
    10.
    发明授权
    Testing for digital signaling 失效
    数字信号测试

    公开(公告)号：US06704277B1

    公开(公告)日：2004-03-09

    申请号：US09474564

    申请日：1999-12-29

    申请人： Sanjay Dabral ,  Ming Zeng ,  Chung-Wai Yue

    发明人： Sanjay Dabral ,  Ming Zeng ,  Chung-Wai Yue

    IPC分类号： H04J100

    CPC分类号： G01R31/001 ,  H04B3/487

    摘要： In an electronic system having logic agents that communicate with each other through one or more signal lines, a method for testing high speed digital signaling on the signal lines is disclosed. The method involves sensing a first crosstalk signal induced by a first digital signal. The first digital signal is driven by a first logic agent into a signal line to communicate with a second agent. The second agent is coupled to receive the first digital signal from the signal line. A logic waveform that represents the digital signal is recorded and/or displayed, based upon the crosstalk signal. The technique may also be used for testing simultaneous bidirectional signaling on the same signal line.

    摘要翻译： 在具有通过一个或多个信号线彼此通信的逻辑代理的电子系统中，公开了一种用于在信号线上测试高速数字信令的方法。 该方法包括感测由第一数字信号引起的第一串扰信号。 第一数字信号由第一逻辑代理驱动到信号线中以与第二代理进行通信。 第二代理被耦合以从信号线接收第一数字信号。 基于串扰信号，记录和/或显示表示数字信号的逻辑波形。 该技术还可用于测试同一信号线上的同步双向信令。