公开(公告)号：US11422812B2

公开(公告)日：2022-08-23

申请号：US16451804

申请日：2019-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F15/76 ,  G06F9/30 ,  G06F9/48 ,  G06F30/34

Abstract: Systems, apparatuses, and methods for implementing as part of a processor pipeline a reprogrammable execution unit capable of executing specialized instructions are disclosed. A processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions. When the processor loads a program for execution, the processor loads a bitfile associated with the program. The processor programs a reprogrammable execution unit with the bitfile so that the reprogrammable execution unit is capable of executing specialized instructions associated with the program. During execution, a dispatch unit dispatches the specialized instructions to the reprogrammable execution unit for execution. The results of other instructions, such as integer and floating point instructions, are available immediately to instructions executing on the reprogrammable execution unit since the reprogrammable execution unit shares the processor registers with the integer and floating point execution units.

公开(公告)号：US20220229712A1

公开(公告)日：2022-07-21

申请号：US17712380

申请日：2022-04-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel ,  David A. Roberts

IPC: G06F11/07 ,  G06N5/04 ,  G06N3/02 ,  G06V10/98

Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.

公开(公告)号：US11030117B2

公开(公告)日：2021-06-08

申请号：US15650252

申请日：2017-07-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Brandon K. Potter ,  Andrew G. Kegel

IPC: G06F12/14 ,  G06F12/10 ,  G06F9/48 ,  G06F9/455 ,  G06F12/0875 ,  G06F9/50

Abstract: A host processor receives an address translation request from an accelerator, which may be trusted or un-trusted. The address translation request includes a virtual address in a virtual address space that is shared by the host processor and the accelerator. The host processor encrypts a physical address in a host memory indicated by the virtual address in response to the accelerator being permitted to access the physical address. The host processor then provides the encrypted physical address to the accelerator. The accelerator provides memory access requests including the encrypted physical address to the host processor, which decrypts the physical address and selectively accesses a location in the host memory indicated by the decrypted physical address depending upon whether the accelerator is permitted to access the location indicated by the decrypted physical address.

公开(公告)号：US20210034252A1

公开(公告)日：2021-02-04

申请号：US16525971

申请日：2019-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel ,  Steven E. Raasch

IPC: G06F3/06 ,  G06F12/0891 ,  G06F16/907

Abstract: An electronic device includes a non-volatile memory and a controller. The controller receives data to be written to the non-volatile memory and determines a type of the data. Based on the type of the data, the controller selects a given duration of the data from among multiple durations of the data in the non-volatile memory. The controller sets values of one or more parameters for writing the data to the non-volatile memory based on the given duration. The controller writes the data to the non-volatile memory using the values of the one or more write parameters.

公开(公告)号：US20190235940A1

公开(公告)日：2019-08-01

申请号：US15884638

申请日：2018-01-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel ,  David A. Roberts

IPC: G06F11/07 ,  G06N5/04 ,  G06K9/03 ,  G06N3/02

CPC classification number: G06F11/076 ,  G06K9/03 ,  G06N3/02 ,  G06N5/04 ,  G06N20/00

Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.

公开(公告)号：US10261916B2

公开(公告)日：2019-04-16

申请号：US15361335

申请日：2016-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov ,  Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1009 ,  G06F12/1027

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.

公开(公告)号：US20170371805A1

公开(公告)日：2017-12-28

申请号：US15191462

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Andrew G. Kegel

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/151 ,  G06F2212/682

Abstract: A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host CPU's virtual address space. Metadata is associated with page table entries (PTEs) and mechanisms use the metadata to limit the number of processing elements that participate in a TLB shootdown operation.

公开(公告)号：US20170277634A1

公开(公告)日：2017-09-28

申请号：US15081379

申请日：2016-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/0811 ,  G06F2212/1024 ,  G06F2212/683 ,  G06F2212/684

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB) that performs operations for handling entries in the TLBs. During operation, the computing device maintains lease values for entries in the TLBs, the lease values representing times until leases for the entries expire, wherein a given entry in the TLB is invalid when the associated lease has expired. The computing device uses the lease value to control operations that are allowed to be performed using information from the entries in the TLBs. In addition, the computing device maintains, in a page table, longest lease values for page table entries indicating when corresponding longest leases for entries in TLBs expire. The longest lease values are used to determine when and if a TLB shootdown is to be performed.

公开(公告)号：US20220382550A1

公开(公告)日：2022-12-01

申请号：US17886855

申请日：2022-08-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F9/30 ,  G06F9/48 ,  G06F30/34

Abstract: Systems, apparatuses, and methods for implementing as part of a processor pipeline a reprogrammable execution unit capable of executing specialized instructions are disclosed. A processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions. When the processor loads a program for execution, the processor loads a bitfile associated with the program. The processor programs a reprogrammable execution unit with the bitfile so that the reprogrammable execution unit is capable of executing specialized instructions associated with the program. During execution, a dispatch unit dispatches the specialized instructions to the reprogrammable execution unit for execution. The results of other instructions, such as integer and floating point instructions, are available immediately to instructions executing on the reprogrammable execution unit since the reprogrammable execution unit shares the processor registers with the integer and floating point execution units.

公开(公告)号：US11140107B2

公开(公告)日：2021-10-05

申请号：US15418369

申请日：2017-01-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew G. Kegel ,  Arkaprava Basu

IPC: G06F15/16 ,  H04L12/58 ,  G06Q10/10 ,  G06F15/173

Abstract: Various messaging systems and methods are disclosed for meeting invitation management. In one aspect, a method of messaging is provided that includes generating a message to invite one or more invitees to a meeting. The message includes an assertion to suppress an auto-responder of the one or more invitees. The message is sent to the one or more invitees. The assertion suppresses the auto-responder of the one or more invitees.