摘要:
A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要:
A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要:
A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp
摘要:
A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
摘要:
A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要:
Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
摘要:
A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要:
A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要:
An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.