公开(公告)号：US07397104B2

公开(公告)日：2008-07-08

申请号：US10778081

申请日：2004-02-17

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L21/00

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

摘要翻译： 提供一种半导体集成电路器件，其包括有源区，与有源区相邻的浅槽隔离，以及形成在有源区中并具有栅极的半导体元件。 有源区的宽度和浅槽隔离的宽度的和构成栅极的栅极宽度方向上的最小间距，并且有源区的宽度被设定为大于最小间距的一半 。

公开(公告)号：US20070141515A1

公开(公告)日：2007-06-21

申请号：US10594244

申请日：2004-03-23

申请人： Akio Sekimoto ,  Masayuki Kojima

发明人： Akio Sekimoto ,  Masayuki Kojima

IPC分类号： G03F7/26

CPC分类号： G03F7/161 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/281 ,  H05K2201/056 ,  H05K2203/066 ,  Y10T29/49117

摘要： In a process for forming a solder mask, a photoimageable ink is coated on a carrier film to form a photoimageable ink layer on the carrier film. The photoimageable ink layer is dried to form a photoimageable resist layer, thereby forming at least one photoimageable resist layer bearing film. The photoimageable resist layer bearing film is laminated on at least one side of a substrate so as to bring the upper surface of the photoimageable resist layer into contact with the substrate. The photoimageable resist layer is exposed to light imagewise through the carrier film. The carrier film is removed from the photoimageable resist layer to form an exposed resist layer. The exposed resist layer is developed to form a developed resist layer. The developed resist layer is cured to form a solder mask on the substrate.

摘要翻译： 在形成焊料掩模的工艺中，将可光成像的油墨涂覆在载体膜上，以在载体膜上形成可光成像的油墨层。 将可光成象的油墨层干燥以形成光致成像抗蚀剂层，从而形成至少一个可光成像抗蚀剂层承载膜。 可光成像抗蚀剂层承载膜层叠在基板的至少一侧上，以使可光成像抗蚀剂层的上表面与基板接触。 可光成像抗蚀剂层通过载体膜成像曝光。 从光致成像抗蚀剂层移除载体膜以形成曝光的抗蚀剂层。 曝光的抗蚀剂层被显影以形成显影的抗蚀剂层。 显影的抗蚀剂层被固化以在基底上形成焊接掩模。

公开(公告)号：US20070037292A1

公开(公告)日：2007-02-15

申请号：US11585137

申请日：2006-10-24

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： G01N1/00

CPC分类号： G01N1/32 ,  H01L21/67201 ,  H01L21/67742 ,  H01L21/67751 ,  Y10T436/25

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g. plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

摘要翻译： 公开了用于处理样品的装置以及使用该装置的方法。 该设备包括用于处理样品（例如等离子体蚀刻设备）的处理设备（a），（b）用于除去由样品处理形成的残余腐蚀性化合物，（c）用于湿法处理样品，（d） 处理样品。 可以进行多个样品的湿法处理。 湿式处理装置可以包括多个湿加工站。 样品可以通过多个湿处理站串联通过，或者可以通过湿处理站并行通过。

公开(公告)号：US07049243B2

公开(公告)日：2006-05-23

申请号：US10754594

申请日：2004-01-12

申请人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

发明人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

IPC分类号： H01L21/302

CPC分类号： H01J37/32082 ,  H01L21/32136

摘要： A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.

摘要翻译： 一种用于蚀刻具有使用电磁波在真空室中产生等离子体的栅极氧化膜的样品的等离子体处理方法，对样品施加rf偏置功率，在样品的充电电压达到击穿之前关断rf偏置功率 栅极氧化膜的电压在样品的充电电压基本上下降之后导通rf偏置功率，并重复rf偏置功率的导通和截止以处理样品。 关断时间至少比导通时间长，并且通过连续供电以在反复打开和关闭rf偏置功率期间产生等离子体而产生等离子体。

公开(公告)号：US06989228B2

公开(公告)日：2006-01-24

申请号：US09917912

申请日：2001-07-31

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： H01L21/461

CPC分类号： H01L21/67069 ,  H01L21/02071 ,  H01L21/31138 ,  H01L21/67028 ,  H01L21/67173 ,  H01L21/67745 ,  Y10S438/963 ,  Y10T436/11 ,  Y10T436/25 ,  Y10T436/2575

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

公开(公告)号：US20050017274A1

公开(公告)日：2005-01-27

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06720234B2

公开(公告)日：2004-04-13

申请号：US10366423

申请日：2003-02-14

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

摘要翻译： 通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。 此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便 具有凸形圆形的截面形状。

公开(公告)号：US06559006B2

公开(公告)日：2003-05-06

申请号：US10157978

申请日：2002-05-31

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质 介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

公开(公告)号：US06492277B1

公开(公告)日：2002-12-10

申请号：US09393893

申请日：1999-09-10

申请人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

发明人： Tetsuo Ono ,  Yasuhiro Nishimori ,  Takashi Sato ,  Naoyuki Kofuji ,  Masaru Izawa ,  Yasushi Goto ,  Ken Yoshioka ,  Hideyuki Kazumi ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takafumi Tokunaga ,  Motohiko Yoshigai

IPC分类号： H01L21302

CPC分类号： H01J37/32082 ,  H01L21/32136

摘要： Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.

摘要翻译： 抑制其等离子体蚀刻对半导体元件的电气损伤。 在通过等离子体蚀刻处理精细图案时，在图案的一部分处的电荷电位达到与所述精细图案互连的栅极氧化膜的击穿电压之前，施加到样本的高频电源被关断 ，然后当图案部分的电荷电位基本上下降时，高频电源被接通。 该开启和关闭控制以重复的操作模式进行。

公开(公告)号：US06436753B1

公开(公告)日：2002-08-20

申请号：US09372007

申请日：1999-08-11

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218244

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth， 引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。