公开(公告)号：US10261935B1

公开(公告)日：2019-04-16

申请号：US15280455

申请日：2016-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Leah Shalev ,  Nafea Bshara ,  Said Bshara

IPC: G06F13/12 ,  G06F13/42 ,  G06F9/455 ,  H04W84/12 ,  H04L29/06

Abstract: Provided are systems and methods for detecting excessive use of a peripheral device by host processes. In various implementations, a peripheral device can include an integrated circuit that includes a traffic counter. The traffic counter can increment based on events received by the peripheral device. The peripheral device can further include an integrated circuit device configured to associate the traffic counter with a process executing on a host device. The integrated circuit device can further initialize a rate counter for the process. When the rate counter reaches a pre-determined time limit, the integrated circuit device can determine that the process is exceeding a usage limit. The integrated circuit device can further read a value from the traffic counter to verify usage of the peripheral device by the process.

公开(公告)号：US10191865B1

公开(公告)日：2019-01-29

申请号：US15099546

申请日：2016-04-14

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Netanel Israel Belgazal ,  Said Bshara ,  Nafea Bshara ,  Adi Habusha

IPC: G06F13/24 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G06F9/455

Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.

公开(公告)号：US10140227B1

公开(公告)日：2018-11-27

申请号：US15087781

申请日：2016-03-31

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Said Bshara ,  Evgeny Schmeilin

IPC: G06F13/28 ,  G06F13/42

Abstract: A first write transaction is received by a device that includes a transaction identifier and a memory location identifier. The memory location identifies a register or a memory location of a device. A value from the register or memory location is read. A second write transaction is sent to a block of host memory. The second write transaction includes the value and the transaction identifier.

公开(公告)号：US09916269B1

公开(公告)日：2018-03-13

申请号：US15099543

申请日：2016-04-14

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Evgeny Schmeilin ,  Said Bshara

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4282

Abstract: A packet header is received from a host and written to a header queue. A direct memory access (DMA) descriptor is received from the host and written to a packet descriptor queue. The DMA descriptor points to packet data in a host memory. The packet data is fetched from host memory and the packet header and the packet data are provided to a network interface.

公开(公告)号：US20240095367A1

公开(公告)日：2024-03-21

申请号：US17662610

申请日：2022-05-09

Applicant: Amazon Technologies, Inc.

Inventor： Said Bshara ,  Nafea Bshara ,  Ali Ghassan Saidi

IPC: G06F21/57

CPC classification number: G06F21/577 ,  G06F2221/034

Abstract: A data guard circuit can be used to verify encryption of the data traffic on a bus between two integrated circuit (IC) devices. The data guard circuit can monitor the data traffic on the bus to analyze the data traffic based on a configuration. The analysis can be performed by sampling the data traffic, and a statistical data pattern can be identified in the sampled data traffic. The statistical data pattern can be compared with a threshold to determine whether the data traffic is encrypted. The data guard circuit can generate a notification if the data traffic is not encrypted as expected so that an appropriate action can be taken to protect the data.

公开(公告)号：US11792299B1

公开(公告)日：2023-10-17

申请号：US17806231

申请日：2022-06-09

Applicant: Amazon Technologies, Inc.

Inventor： Said Bshara ,  Alan Michael Judge ,  Erez Izenberg ,  Julien Ridoux ,  Joshua Benjamin Levinson ,  Anthony Nicholas Liguori ,  Nafea Bshara

IPC: H04L9/40 ,  H04L67/60 ,  H04L67/14 ,  G06F9/50

CPC classification number: H04L67/60 ,  G06F9/5038 ,  H04L63/0428 ,  H04L67/14

Abstract: Various embodiments of apparatuses and methods for multi-cast, multiple unicast, and unicast distribution of messages with time synchronized delivery are described. In some embodiments, the disclosed system and methods include a reference timekeeper providing a reference clock to one or more host computing devices. The one or more host computing devices host compute instances, and also contain respective isolated timing hardware outside the control of the compute instances. The isolated timing hardware of the one or more host computing devices then receive respective packets, and obtain the same time to deliver the respective packets. Each isolated timing hardware provides either the packet, or information to access the packet, to its respective destination compute instance subsequent to determining that the same specified time to deliver the packet has occurred. Thus, the respective packets are delivered near simultaneously to the one or more destination compute instances.

公开(公告)号：US20230308378A1

公开(公告)日：2023-09-28

申请号：US17705157

申请日：2022-03-25

Applicant: Amazon Technologies, Inc.

Inventor： Alan Michael Judge ,  Said Bshara ,  Julien Ridoux ,  Joshua Benjamin Levinson ,  David James Goodell ,  Erez Izenberg ,  Anthony Nicholas Liguori

IPC: H04L43/106 ,  H04L43/0852

CPC classification number: H04L43/106 ,  H04L43/0852 ,  H04L2212/00

Abstract: Various embodiments of apparatuses and methods for trusted and/or attested packet timestamping are described. In some embodiments, the disclosed system and methods include a reference timekeeper providing a reference clock to host computing devices. The host computing devices host compute instances using a first set of computing resources, and also contain isolated timing hardware utilizing a different set of computing resources. The isolated timing hardware sets a hardware clock based on a signal corresponding to the reference clock from the reference timekeeper. The isolated timing hardware then receives a packet from a particular compute instance, creates a timestamp for the packet based at least in part on the hardware clock, where the timestamp is outside the control of the compute instances, and sends the packet and the timestamp through a data network to transmit to a packet destination.

公开(公告)号：US20230221971A1

公开(公告)日：2023-07-13

申请号：US18186748

申请日：2023-03-20

Applicant: Amazon Technologies, Inc.

Inventor： Barak Wasserstrom ,  Said Bshara ,  Akram Baransi ,  Omri Itach ,  Tal Zilcer

IPC: G06F13/42 ,  G06F13/10 ,  G06F13/24

CPC classification number: G06F13/4221 ,  G06F13/24 ,  G06F13/105

Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

公开(公告)号：US11599490B1

公开(公告)日：2023-03-07

申请号：US15913786

申请日：2018-03-06

Applicant: Amazon Technologies, Inc.

Inventor： Georgy Machulsky ,  Nafea Bshara ,  Netanel Israel Belgazal ,  Evgeny Schmeilin ,  Said Bshara

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: A packet header is received from a host and written to a header queue. A direct memory access (DMA) descriptor is received from the host and written to a packet descriptor queue. The DMA descriptor points to packet data in a host memory. The packet data is fetched from host memory and the packet header and the packet data are provided to a network interface.

公开(公告)号：US20190384710A1

公开(公告)日：2019-12-19

申请号：US16110748

申请日：2018-08-23

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/0817 ,  G06F12/0855 ,  G06F12/0831 ,  G11C7/10

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.