公开(公告)号：US6124665A

公开(公告)日：2000-09-26

申请号：US345112

申请日：1999-07-06

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J3/02 ,  H01J9/02 ,  H01J1/02

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2329/00

Abstract: A method of fabricating row lines over a field emission array. The method employs only two mask steps to define row lines and pixel openings through selected regions of each of the row lines. In accordance with the method of the resent invention, a layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material. A layer of passivation material is then disposed over the layer of conductive material. In one embodiment of the method, a first mask may be employed to remove passivation material and conductive material from between adjacent rows of pixels and from substantially above each of the pixels of the field emission array. A second mask is employed to remove semiconductive material from between the adjacent rows of pixels. In another embodiment of the method, a first mask is employed to facilitate removal of passivation material, conductive material, and semiconductive material from between adjacent rows of pixels of the field emission array. A second mask is employed to facilitate the removal of passivation material and conductive material from the desired areas of pixel openings. The present invention also includes field emission arrays having a semiconductive grid and a relatively thin passivation layer exposed between adjacent row lines.

Abstract translation: 一种在场发射阵列上制造行线的方法。 该方法仅采用两个掩模步骤来通过每条行线的选定区域来定义行线和像素开口。 根据本发明的方法，将导电材料层设置在半导体材料格栅的基本上平坦化的表面上。 然后将一层钝化材料设置在导电材料层上。 在该方法的一个实施例中，可以使用第一掩模来从相邻的像素行之间以及从场发射阵列的每个像素的大致上方去除钝化材料和导电材料。 采用第二掩模从相邻的像素行之间移除半导体材料。 在该方法的另一个实施例中，使用第一掩模以便于从场致发射阵列的相邻行像素之间移除钝化材料，导电材料和半导体材料。 使用第二掩模来促进从像素开口的期望区域去除钝化材料和导电材料。 本发明还包括具有半导电栅格的场发射阵列和暴露在相邻行线之间的相对薄的钝化层。

公开(公告)号：US07402512B2

公开(公告)日：2008-07-22

申请号：US11153091

申请日：2005-06-15

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868 ,  H01L21/76877 ,  H01L29/456

Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

Abstract translation: 形成在硅衬底的接合区域上的高纵横比接触结构包括散布有硅化钛层的钛，其沉积在接触开口中并直接接触衬底的上表面。 在沉积期间从SiH 4 Si的添加中CVD钛的掺杂减少了在随后的硅化反应期间底物硅的消耗，其中钛与硅反应形成提供低电阻的硅化钛层 接合区域和硅衬底之间的电接触。 接触结构还包括氮化钛接触填料，其沉积在接触开口中并基本上填充整个接触开口。

公开(公告)号：US07393563B2

公开(公告)日：2008-07-01

申请号：US11394989

申请日：2006-03-30

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

IPC: C23C16/14 ,  C23C16/24

CPC classification number: H01L21/28518 ,  C23C16/42 ,  H01L21/28556

Abstract: Chemical vapor deposition methods of forming titanium suicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.

Abstract translation: 公开了在衬底上形成包括层的硅化钛的化学气相沉积方法。 TiCl 4 S和至少一种硅烷首先以等于或高于TiCl 4的第一体积比与硅烷一起进料到室中，持续第一段时间。 该比例足够高以避免钛硅化物在衬底上的可测量沉积。 或者，在第一时间段内没有可测量的硅烷进料到室中。 无论如何，在第一阶段之后，将TiCl 4 S和至少一种硅烷以等于或低于TiCl 4的第二体积比与硅烷一起进料到室中，持续第二阶段 时间。 如果在第一时间段内进料至少一种硅烷，则第二体积比率低于第一体积比。 无论如何，第二次进料对于等离子体有效地提高了化学气相沉积在基底上的包含硅的硅化钛。

公开(公告)号：US07354329B2

公开(公告)日：2008-04-08

申请号：US11207010

申请日：2005-08-17

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J9/00 ,  H01J9/02

CPC classification number: H01J9/025 ,  G09G3/22 ,  G09G2310/0221 ,  H01J1/3042

Abstract: A substrate is provided and is configurable into a base plate for a field emission display. A plurality of discrete, segmented regions of field emitter tips are formed by at least removing portions of the substrate. The regions are electrically isolated into separately-addressable regions. In another embodiment, a plurality of field emitters are formed from material of the substrate and arranged into more than one demarcated, independently-addressable region of emitters.

Abstract translation: 提供基板并且可配置成用于场发射显示器的基板。 通过至少去除衬底的部分来形成多个离散的，分段的场发射器尖端的区域。 这些区域被电隔离成可单独寻址的区域。 在另一个实施例中，多个场致发射体由衬底的材料形成并且被布置成多于一个分开的，可独立寻址的发射器区域。

公开(公告)号：US07105992B2

公开(公告)日：2006-09-12

申请号：US10666236

申请日：2003-09-19

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J1/304 ,  H01J19/24

CPC classification number: H01J3/021 ,  H01J1/3044 ,  H01J9/185 ,  H01J29/481 ,  H01J31/127

Abstract: An FED and a method of manufacture are provided. The FED includes a cathode assembly containing an improved column line structure. The column line structure includes a conductive structure formed on a substrate. A resistive layer is formed on the conductive structure, and an insulator layer is formed partly over the resistive layer. The contact between the base of the emitter tips and the addressing column line is achieved through a lateral side that is not covered by the insulator layer. The insulator layer helps reduce the possibility of electrical shorting between the addressing column line and the row line structure of the cathode assembly. The insulator layer on top of the addressing column line will allow the use of a thinner subsequent dielectric layer. This thinner dielectric layer, which supports the grid, will provide a lower RC time constant and help achieve better video rate operation. The thinner dielectric layer also will result in smaller grid openings above the tips. This will provide for better beam spots, and, therefore, better image resolution. The thinner dielectric layer will require less applied voltage to extract electrons from the tips, resulting in lower power consumption for the FED.

Abstract translation: 提供FED和制造方法。 FED包括具有改进的柱线结构的阴极组件。 列线结构包括形成在基板上的导电结构。 在导电结构上形成电阻层，部分地在电阻层上形成绝缘体层。 通过未被绝缘体层覆盖的侧面来实现发射极尖端的基极与寻址列线之间的接触。 绝缘体层有助于减少寻址列线和阴极组件的行线结构之间的电短路的可能性。 在寻址列线顶部的绝缘体层将允许使用更薄的后续介电层。 支持电网的这种较薄的介质层将提供较低的RC时间常数，有助于实现更好的视频速率操作。 更薄的介电层也将导致尖端上方的较小的栅极开口。 这将提供更好的光束点，因此，更好的图像分辨率。 更薄的电介质层将需要更少的施加电压以从尖端提取电子，导致FED的较低功耗。

公开(公告)号：US20050287898A1

公开(公告)日：2005-12-29

申请号：US11207010

申请日：2005-08-17

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: G09G3/22 ,  H01J1/304 ,  H01J9/02 ,  H01J9/00 ,  H01J9/04

CPC classification number: H01J9/025 ,  G09G3/22 ,  G09G2310/0221 ,  H01J1/3042

Abstract: Methods of forming base plates for field emission display (FED) devices, methods of forming field emission display (FED) devices, and resultant FED base plate and device constructions are described. In one embodiment, a substrate is provided and is configurable into a base plate for a field emission display. A plurality of discrete, segmented regions of field emitter tips are formed by at least removing portions of the substrate. The regions are electrically isolated into separately-addressable regions. In another embodiment, a plurality of field emitters are formed from material of the substrate and arranged into more than one demarcated, independently-addressable region of emitters. Address circuitry is provided and is operably coupled with the field emitters and configured to independently address individual regions of the emitters. In yet another embodiment, a monolithic addressable matrix of rows and columns of field emitters is provided and has a perimetral edge defining length and width dimensions of the matrix. The matrix is partitioned into a plurality of discretely-addressable sub-matrices of field emitters. Row and column address lines are provided and are operably coupled with the matrix and collectively configured to address the field emitters. At least one of the row or column address lines has a length within the matrix which is sufficient to address less than all of the field emitters which lie in the direction along which the address line extends within the matrix.

Abstract translation: 描述了形成场致发射显示器（FED）器件的基板的形成方法，场致发射显示器（FED）器件的形成方法，以及所得到的FED基板和器件结构。 在一个实施例中，提供了衬底并且可配置成用于场致发射显示器的基板。 通过至少去除衬底的部分来形成多个离散的，分段的场发射器尖端的区域。 这些区域被电隔离成可单独寻址的区域。 在另一个实施例中，多个场致发射体由衬底的材料形成并且被布置成多于一个分开的，可独立寻址的发射器区域。 提供地址电路并且与现场发射器可操作地耦合并且被配置为独立地对发射器的各个区域进行寻址。 在另一个实施例中，提供了场致发射体的列和列的单片可寻址矩阵，并且具有限定矩阵的长度和宽度尺寸的周边边缘。 矩阵被分割成场发射器的多个可离散寻址的子矩阵。 提供行和列地址线并且与矩阵可操作地耦合并且共同配置为寻址场发射器。 行或列地址行中的至少一个具有矩阵内的长度，该长度足以寻址小于位于矩阵内的地址线延伸的方向上的所有场发射器。

公开(公告)号：US06957994B2

公开(公告)日：2005-10-25

申请号：US10654226

申请日：2003-09-02

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J9/02 ,  H01J9/00

CPC classification number: H01J9/025

Abstract: An emission structure includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive element positioned adjacent the resistor. The conductive element may contact the resistor. A method for fabricating the emission structure includes forming at least one conductive line, depositing at least one layer of semiconductive or conductive material over and laterally adjacent the at least one conductive line, and forming a hard mask in recessed areas of the surface of the uppermost material layer. The underlying material layer or layers are patterned through the hard mask, exposing substantially longitudinal center portions of the conductive lines. The remaining semiconductive or conductive material is patterned to form the emitter tip and resistor. At least the substantially central longitudinal portion of the conductive trace is removed to form the conductive element.

Abstract translation: 发射结构包括其上具有至少一个发射极尖端的电阻器和邻近电阻器定位的至少一个基本垂直定向的导电元件。 导电元件可以接触电阻器。 一种用于制造发射结构的方法包括形成至少一条导电线，在至少一条导电线上方并横向相邻地沉积至少一层半导体或导电材料，并在最上面的表面的凹陷区域中形成硬掩模 材料层。 通过硬掩模对下面的材料层或图案进行图案化，暴露导电线的基本上纵向的中心部分。 剩余的半导体或导电材料被图案化以形成发射极尖端和电阻器。 至少导电迹线的基本中心纵向部分被去除以形成导电元件。

公开(公告)号：US20050233577A1

公开(公告)日：2005-10-20

申请号：US11153091

申请日：2005-06-15

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/45

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868 ,  H01L21/76877 ,  H01L29/456

Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

公开(公告)号：US06831398B2

公开(公告)日：2004-12-14

申请号：US10430452

申请日：2003-05-06

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J130

CPC classification number: H01J9/025

Abstract: Row lines include a layer of semiconductive material, conductive material over the layer of semiconductive material, and a passivation layer over the conductive material. The passivation layer contacts a dielectric layer that underlies the semiconductive layer of an emission device at locations that are laterally adjacent to edges of the layer of semiconductive material. One or more pixel openings are defined through the passivation layer, the conductive material, and the underlying semiconductive grid. At least one emitter tip may be exposed through each of the passivation layer, the conductive material, and the layer of semiconductive material. Such row lines may be included in field emission arrays and field emission devices.

Abstract translation: 行线包括半导体材料层，半导体材料层上的导电材料和导电材料上的钝化层。 钝化层在横向邻近半导体材料层的边缘的位置处接触位于发射器件的半导体层下面的介电层。 通过钝化层，导电材料和下面的半导电栅格限定一个或多个像素开口。 可以通过钝化层，导电材料和半导体材料层中的每一个露出至少一个发射极尖端。 这样的行线可以包括在场发射阵列和场发射装置中。

公开(公告)号：US06767823B2

公开(公告)日：2004-07-27

申请号：US10094580

申请日：2002-03-06

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

IPC: H01L214763

CPC classification number: H01L21/28518 ,  C23C16/42 ,  H01L21/28556

Abstract: Chemical vapor deposition methods of forming titanium silicide comprising layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide comprising layer on the substrate.

Abstract translation: 公开了在衬底上形成包含层的硅化钛的化学气相沉积方法。 首先将TiCl 4和至少一种硅烷以等于或高于TiCl 4与硅烷的第一体积比率进料到室中。 该比例足够高以避免钛硅化物在衬底上的可测量沉积。 或者，在第一时间段内没有可测量的硅烷进料到室中。 无论如何，在第一阶段之后，将TiCl 4和至少一种硅烷以等于或低于第二体积比的TiCl 4与硅烷进料至室中第二时间段。 如果在第一时间段内进料至少一种硅烷，则第二体积比率低于第一体积比。 无论如何，第二次进料对于等离子体有效地增强化学气相沉积在基底上的包含硅化钛的层。