公开(公告)号：US06603339B2

公开(公告)日：2003-08-05

申请号：US10017744

申请日：2001-12-14

申请人： Francois I. Atallah ,  Anthony Correale, Jr.

发明人： Francois I. Atallah ,  Anthony Correale, Jr.

IPC分类号： H03K3017

CPC分类号： H03K5/1565 ,  H03K2005/00039

摘要： An incoming signal's duty cycle is transformed to a known value by a first programmable duty cycle generator, and the output of the first programmable duty cycle generator is applied to a second programmable duty cycle generator which includes multiple stages which provide multiple duty cycle tap point outpoints, each having a different known value of a precise duty cycle, wherein the leading edges or trailing edges of the multiple duty cycle tap point output signals are phase aligned with respect to each other by voltage controlled delay matching elements which are replicas of the stages of the second duty cycle generator.

摘要翻译： 输入信号的占空比通过第一可编程占空比发生器转换为已知值，并且第一可编程占空比发生器的输出被施加到第二可编程占空比发生器，该第二可编程占空比发生器包括提供多个占空比分接点外点的多个级 ，每个具有不同的已知值的精确占空比，其中多个占空比抽头点输出信号的前沿或后沿相对于彼此相互对准，该电压控制的延迟匹配元件是复制的阶段 第二个占空比发生器。

公开(公告)号：US6001662A

公开(公告)日：1999-12-14

申请号：US982440

申请日：1997-12-02

申请人： Anthony Correale, Jr. ,  James Norris Dieffenderfer ,  Trevor Scott Garner ,  Ronald William Kohake ,  Ketan Vitthal Patel

发明人： Anthony Correale, Jr. ,  James Norris Dieffenderfer ,  Trevor Scott Garner ,  Ronald William Kohake ,  Ketan Vitthal Patel

IPC分类号： G05B19/418 ,  H01L21/00

CPC分类号： G05B19/41875 ,  G05B2219/33323 ,  Y02P90/14 ,  Y02P90/16 ,  Y02P90/22

摘要： A method and system for manufacturing integrated circuit devices having multiple memory units embedded therein. Initially, a single reusable configurable test circuit is fabricated within an integrated circuit device. A number and type of each memory unit embedded within the integrated circuit device are then identified. Finally, the single reusable configurable test circuit is configured, in response to the identifying of a number and type of each memory unit, such that only one test circuit is required for use with multiple integrated circuit devices having multiple diverse memory units embedded therein. The single reusable configurable test circuit can be placed within or outside a fixed core of the integrated circuit device. In addition, the single reusable configurable test circuit can include array built-in self test (ABIST) controller which includes a hierarchical memory configuration that includes a state machine, address counter, compare register and data pattern generator.

摘要翻译： 一种用于制造具有嵌入其中的多个存储器单元的集成电路器件的方法和系统。 最初，在集成电路装置内制造单个可重复使用的可配置测试电路。 然后识别嵌入集成电路设备内的每个存储单元的数量和类型。 最后，单个可重复使用的可配置测试电路被配置为响应于每个存储器单元的数量和类型的识别，使得仅需要一个测试电路用于具有嵌入其中的多个不同存储器单元的多个集成电路器件。 单个可重复使用的可配置测试电路可以放置在集成电路器件的固定磁芯内或外部。 此外，单个可重复使用的可配置测试电路可以包括阵列内置自检（ABIST）控制器，其包括分层存储器配置，其包括状态机，地址计数器，比较寄存器和数据模式发生器。

公开(公告)号：US4998221A

公开(公告)日：1991-03-05

申请号：US429670

申请日：1989-10-31

申请人： Anthony Correale, Jr.

发明人： Anthony Correale, Jr.

IPC分类号： G06F9/38 ,  G06F12/00 ,  G06F12/08 ,  G11C7/00 ,  G11C7/10

CPC分类号： G06F12/0888 ,  G06F12/0853 ,  G06F12/0859 ,  G06F9/3824 ,  G11C7/00 ,  G11C7/1006

摘要： The present invention utilizes bypass circuitry to shorten the cycle time of a cache memory by shortening the time required to perform a write through read operation (WTR). The bypass circuitry senses when a WTR operation will occur by comparing the encoded read and write addresses to determine when the encoded addresses are equal. When the encoded addresses are equal, a WTR operation is requested and the bypass circuitry sends the data to be written into memory to both the write address location and the cache output buffer. The bypass circuitry does not wait to access the data from the memory cells through the read decode, rather, it directly sends the data to the output buffer. The bypass circuitry provides a parallel read and write operations instead of serial operations during a WTR, thereby shortening the machine cycle time. The bypass circuitry also prevents glitches from being sent to the output when the WTR operation is complete by accessing the memory cells through the read decode even though the cells are disconnected from the output buffer during the WTR operation. The cycle time is be shortened by making the longest operation of the memory shorter.

公开(公告)号：US08136062B2

公开(公告)日：2012-03-13

申请号：US12200016

申请日：2008-08-28

申请人： Paul M. Steinmetz ,  Benjamin J. Bowers ,  Anthony Correale, Jr. ,  Irfan Rashid ,  Matthew W. Baker

发明人： Paul M. Steinmetz ,  Benjamin J. Bowers ,  Anthony Correale, Jr. ,  Irfan Rashid ,  Matthew W. Baker

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist.

摘要翻译： 公开了在闭环1×N系统中重新组合分层表示的实施例。 一些实施例包括从1×N构建块的分层表示形成平坦网表，为平坦网表创建属性，以及例如通过逻辑设计工具的操作，改变平面网表的一个或多个元素，合成 工具，物理设计工具或时序分析工具。 实施例还包括生成反映改变的元素的1×N构建块的第二分层表示。 另外的实施例包括具有1×N编译器和重组器的装置。 1×N编译器可以为1×N构建块的分层表示的元素的平坦网表创建属性。 重组器可以使用这些属性来创建1×N构建块的第二层次表示，其反映元素的变化到平坦网表。

公开(公告)号：US07904847B2

公开(公告)日：2011-03-08

申请号：US12032745

申请日：2008-02-18

申请人： Anthony Correale, Jr. ,  Nishith Rohatgi ,  Benjamin John Bowers

发明人： Anthony Correale, Jr. ,  Nishith Rohatgi ,  Benjamin John Bowers

IPC分类号： G06F17/50 ,  H03K17/693 ,  H03K19/00 ,  H03K3/00 ,  H03K3/356

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are interconnected. Next, an input signal state data file is generated which provides all of the possible input states for the circuit. A determination is made of which devices in the circuit are in an OFF state for each of the input signal states provided. Then the leakage current for each of these devices in the OFF state is computed for each of the input signal states.

摘要翻译： 本发明提供了一种用于确定具有多个器件的CMOS电路中的漏电流的方法。 它包括读取描述电路的网表的步骤，并包括电路中这两个设备的信息以及这些设备如何互连。 接下来，生成输入信号状态数据文件，其提供电路的所有可能的输入状态。 根据所提供的每个输入信号状态，确定电路中哪些装置处于OFF状态。 然后针对每个输入信号状态计算处于OFF状态的这些器件中的每一个的漏电流。

公开(公告)号：US07784012B2

公开(公告)日：2010-08-24

申请号：US11849908

申请日：2007-09-04

申请人： Anthony Correale, Jr.

发明人： Anthony Correale, Jr.

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A standard cell library including a first set of cells including mixed threshold voltage cells. Each mixed threshold voltage cell includes a first threshold voltage device having a first threshold voltage and a second threshold voltage device having a second threshold voltage, in which the first threshold voltage is different from the second threshold voltage. The standard cell library further includes a second set of cells including non-mixed threshold voltage cells. Each non-mixed threshold voltage cell includes threshold voltage devices having a same threshold voltage. A mixed threshold voltage cell has substantially a same footprint as a non-mixed threshold voltage cell.

摘要翻译： 包括包括混合阈值电压单元的第一组单元的标准单元库。 每个混合阈值电压单元包括具有第一阈值电压的第一阈值电压器件和具有第二阈值电压的第二阈值电压器件，其中第一阈值电压与第二阈值电压不同。 标准单元库还包括第二组单元格，包括非混合阈值电压单元。 每个非混合阈值电压单元包括具有相同阈值电压的阈值电压器件。 混合阈值电压单元具有与非混合阈值电压单元基本相同的占空比。

公开(公告)号：US07779237B2

公开(公告)日：2010-08-17

申请号：US11776222

申请日：2007-07-11

申请人： Anthony Correale, Jr. ,  Kenichi Tsuchiya

发明人： Anthony Correale, Jr. ,  Kenichi Tsuchiya

IPC分类号： G06F9/30 ,  G06F9/302

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3296 ,  G06F9/30145 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/172

摘要： A method, system and processor for adaptively and selectively controlling the instruction execution frequency of a data processor. Processing logic or a software compiler determines when a number of first-type instructions, requiring longer execution latency, are scheduled to be executed. The logic/compiler then triggers the CPM unit to automatically switch the execution frequency of the instruction processor from a first frequency that is optimal for processing regular-type instructions to a second, pre-established lower frequency that is optimal for processing the first-type instructions, to enable more efficient execution and higher execution throughput of the number of first-type operations within the processor. When the first-type instructions have completed execution, the processor's instruction execution frequency is returned to the first optimal frequency.

摘要翻译： 一种用于自适应地和选择性地控制数据处理器的指令执行频率的方法，系统和处理器。 处理逻辑或软件编译器确定何时调度执行需要更长执行延迟的第一类指令。 逻辑/编译器然后触发CPM单元自动地将指令处理器的执行频率从处理规则类型指令的最佳的第一频率切换到对于处理第一类型的处理最佳的第二预先建立的较低频率 指令，以实现处理器内第一类型操作数量的更高效的执行和更高的执行吞吐量。 当第一类指令完成执行时，处理器的指令执行频率返回到第一最佳频率。

公开(公告)号：US20100058269A1

公开(公告)日：2010-03-04

申请号：US12201685

申请日：2008-08-29

申请人： Matthew W. Baker ,  Benjamin J. Bowers ,  Anthony Correale, Jr. ,  Irfan Rashid ,  Paul M. Steinmetz

发明人： Matthew W. Baker ,  Benjamin J. Bowers ,  Anthony Correale, Jr. ,  Irfan Rashid ,  Paul M. Steinmetz

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second 1×N building block. The association enables the first 1×N building block to inherit alterations of attributes of the second 1×N building block and enables unique alterations of attributes of the first 1×N building block which differ from the second 1×N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1×N building blocks, an attribute creator that creates a set of attributes and enables one of the 1×N building blocks to inherit parent attributes and comprise child attributes.

摘要翻译： 公开了在闭环1×N系统中创建用于重新使用1×N构建块的父子关系的实施例。 一些方法包括生成IC设计的表示，将第一个1×N构建块插入到该表示中，以及在第一个1×N构建块和第二个1×N构建块之间建立关联。 该关联使得第一个1×N构建块能够继承第二个1×N构建块的属性的改变，并且使得与第二个1×N构建块不同的第一个1×N构建块的属性的唯一改变。 另外的实施例包括具有等效确定器的装置，以确定两个1×N构建块之间的逻辑等价，创建一组属性的属性创建者，并且使得1×N构建块中的一个可以继承父属性并且包括子属性 。

公开(公告)号：US07619923B2

公开(公告)日：2009-11-17

申请号：US11950459

申请日：2007-12-05

申请人： Anthony Correale, Jr. ,  Rahul K. Nadkarni

发明人： Anthony Correale, Jr. ,  Rahul K. Nadkarni

IPC分类号： G11C11/34

CPC分类号： G11C7/12 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18

摘要： A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the cells through the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier.

摘要翻译： 用于降低分级位线架构中的电流泄漏的电路包括具有晶体管的读出放大器，读出放大器耦合到存储器阵列中的单元的位线，该读出放大器配置用于检测来自其中一个单元的存储数据; 具有晶体管的输出锁存器，所述输出锁存器选择性地耦合到具有逻辑状态的所述读出放大器的全局位线，所述输出锁存器被配置为经由所述全局位线选择性地从所述单元之一读出存储的数据; 以及耦合在所述读出放大器和所述输出锁存器之间的传输选通装置，用于选择性地将所述读出放大器耦合到所述输出锁存器，以相应地消除第一泄漏路径并形成第二泄漏路径，所述第一泄漏路径位于所述读出放大器和所述输出锁存器 ，形成在读出放大器内的第二泄漏路径。

公开(公告)号：US07470613B2

公开(公告)日：2008-12-30

申请号：US11619748

申请日：2007-01-04

申请人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

发明人： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC分类号： H01L21/4763

CPC分类号： H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

摘要翻译： 一种用于形成互连结构的方法，所述互连结构包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下导电衬垫在侧面和底部 的下层电线; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。