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    Memory error protection using addressable dynamic ram data locations
    22.
    发明授权
    Memory error protection using addressable dynamic ram data locations 有权
    使用可寻址的动态RAM数据位置进行内存错误保护

    公开(公告)号：US08843805B1

    公开(公告)日：2014-09-23

    申请号：US13422934

    申请日：2012-03-16

    申请人： Deepak Goel ,  Jeffrey G. Libby ,  Anurag P. Gupta ,  Abhijit Ghosh ,  David J. Ofelt

    发明人： Deepak Goel ,  Jeffrey G. Libby ,  Anurag P. Gupta ,  Abhijit Ghosh ,  David J. Ofelt

    IPC分类号： G11C29/00 ,  G11C7/24 ,  G06F11/10

    CPC分类号： G11C7/24 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1048 ,  G11C11/401

    摘要： In general, techniques are described for efficiently and transparently partitioning a physical address space of a DRAM part lacking dedicated error protection circuitry to supply addressable error protection bytes for use in detecting and/or correcting bit errors elsewhere present in the physical address space. In one example, a network device includes a DRAM and a memory controller that receives a write command to write data to the DRAM. An address translation module of the memory controller logically partitions the DRAM to define a plurality of physically addressable sections that includes an error protection section for storing error protection bits and one or more data storage sections. The memory controller defines a contiguous logical address space representing the data storage sections. A DRAM controller of the network device communicates with the DRAM to store the data to one of the data storage sections in accordance with the contiguous logical address space.

    摘要翻译： 通常，描述了技术以有效和透明地划分缺少专用的错误保护电路的DRAM部分的物理地址空间，以提供用于检测和/或校正物理地址空间中存在的位错误的可寻址的错误保护字节。 在一个示例中，网络设备包括DRAM和存储器控制器，其接收写入数据到DRAM的写命令。 存储器控制器的地址转换模块逻辑地分区DRAM以定义多个物理寻址部分，其包括用于存储错误保护位和一个或多个数据存储部分的错误保护部分。 存储器控制器定义表示数据存储部分的连续的逻辑地址空间。 网络设备的DRAM控制器与DRAM通信，以根据连续的逻辑地址空间将数据存储到数据存储部分之一。

    Use of cache to reduce memory bandwidth pressure with processing pipeline
    23.
    发明授权
    Use of cache to reduce memory bandwidth pressure with processing pipeline 有权
    使用缓存来减少内存带宽压力与处理流水线

    公开(公告)号：US08627007B1

    公开(公告)日：2014-01-07

    申请号：US12607510

    申请日：2009-10-28

    申请人： Jianhui Huang ,  Sharada Yeluri ,  Jean-Marc Frailong ,  Jeffrey G. Libby ,  Anurag P. Gupta ,  Paul Coelho

    发明人： Jianhui Huang ,  Sharada Yeluri ,  Jean-Marc Frailong ,  Jeffrey G. Libby ,  Anurag P. Gupta ,  Paul Coelho

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0855 ,  G06F12/0815 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/12 ,  Y02D10/13

    摘要： A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.

    摘要翻译： 数据读/写系统包括系统时钟，单端口存储器，与单端口存储器分开的高速缓存存储器，以及耦合到指令流水线的控制器。 控制器经由指令流水线接收第一数据以写入单端口存储器的地址，并且经由指令流水线接收从单端口存储器读取第二数据的请求。 控制器将第一数据存储在高速缓冲存储器中，并且在系统时钟的一个或多个第一时钟周期期间从高速缓冲存储器或单端口存储器检索第二数据。 控制器从高速缓冲存储器复制第一数据，并且在系统时钟的不同于一个或多个第一时钟周期的第二时钟周期期间将第一数据存储在单端口存储器中的地址处。

    Maintaining data unit order in a network switching device
    24.
    发明授权
    Maintaining data unit order in a network switching device 有权
    维护网络交换设备中的数据单元顺序

    公开(公告)号：US07924860B1

    公开(公告)日：2011-04-12

    申请号：US12343318

    申请日：2008-12-23

    申请人： Jean-Marc Frailong ,  Sharada Yeluri ,  Anurag P. Gupta ,  Jeffrey G. Libby ,  Edwin Su

    发明人： Jean-Marc Frailong ,  Sharada Yeluri ,  Anurag P. Gupta ,  Jeffrey G. Libby ,  Edwin Su

    IPC分类号： H04L12/56

    CPC分类号： H04L49/552 ,  H04L49/90 ,  H04L49/9047 ,  H04L49/9094

    摘要： Data units received by a network device may be classified into traffic flow classes in which the determined traffic flow class for a data unit may be dynamically refined as the data unit is processed by the network device. A dispatch component of the network device may receive data units associated with traffic flow classes. Parallel processing engines of the network device may receive the data units from the dispatch component and may generate, for a least one of the data units, a plurality of dynamically refined indications of the traffic flow class to which the data unit belongs. Additionally, an ordering component of the network device may include a plurality of re-order queues, where the at least one data unit successively progresses through at least two of the re-order queues in an order defined by the plurality of dynamically refined indications of the traffic flow class.

    摘要翻译： 由网络设备接收的数据单元可以被分类为业务流类别，其中所确定的数据单元的业务流类别可以由网络设备处理数据单元时动态地改进。 网络设备的调度组件可以接收与业务流类别相关联的数据单元。 网络设备的并行处理引擎可以从调度组件接收数据单元，并且可以为数据单元中的至少一个数据单元生成数据单元所属的业务流类别的多个动态精确的指示。 另外，网络设备的排序组件可以包括多个重新排序队列，其中至少一个数据单元以由多个动态精简指示定义的顺序连续地进行至少两个重排队列 交通流量类。

    SYSTEM AND METHOD FOR FAST BRANCHING USING A PROGRAMMABLE BRANCH TABLE
    25.
    发明申请
    SYSTEM AND METHOD FOR FAST BRANCHING USING A PROGRAMMABLE BRANCH TABLE 有权
    使用可编程分支表快速分支的系统和方法

    公开(公告)号：US20100161949A1

    公开(公告)日：2010-06-24

    申请号：US12342851

    申请日：2008-12-23

    申请人： Anurag P. Gupta ,  John Keen ,  Jeffrey G. Libby ,  Jean-Marc Frailong ,  Avanindra Godbole ,  Sharada Yeluri

    发明人： Anurag P. Gupta ,  John Keen ,  Jeffrey G. Libby ,  Jean-Marc Frailong ,  Avanindra Godbole ,  Sharada Yeluri

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30058 ,  G06F9/262 ,  G06F9/3885

    摘要： Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.

    摘要翻译： 与本发明一致的方法和系统提供了可编程表，其允许软件定义多个分支功能，每个分支功能将条件代码的向量映射到分支偏移。 该技术允许灵活的多路分支功能，使用可由程序员指定的条件分支结果表。 任何指令都可以指定任意条件表达式的计算，以计算条件代码的值，并可以选择特定的分支函数。 当处理器执行指令时，处理器的算术/逻辑功能单元评估条件表达式，然后处理器根据指定的分支函数执行分支操作。

    Acquisition of multiple synchronization objects within a computing device
    26.
    发明授权
    Acquisition of multiple synchronization objects within a computing device 有权
    在计算设备内获取多个同步对象

    公开(公告)号：US08954409B1

    公开(公告)日：2015-02-10

    申请号：US13240259

    申请日：2011-09-22

    申请人： Oren Kerem ,  Jeffrey G. Libby ,  Deepak Goel ,  David J. Ofelt ,  Anurag P. Gupta

    发明人： Oren Kerem ,  Jeffrey G. Libby ,  Deepak Goel ,  David J. Ofelt ,  Anurag P. Gupta

    IPC分类号： G06F17/00

    CPC分类号： G06F17/30949 ,  G06F17/30348

    摘要： In general, techniques of the present disclosure relate to synchronizing concurrent access to multiple portions of a data structure. In one example, a method includes, sequentially selecting a plurality of requests from a request queue, wherein at least one of the requests specifies a plurality of requested synchronization objects for corresponding candidate portions of a data structure to which to apply an operation associated with a data element. The method also includes querying one or more sets of identifiers to determine whether one or more of the requested synchronizations objects specified by the selected request are acquirable. The method also includes acquiring each of the requested synchronization objects that are acquirable. The method includes, responsive to acquiring all of the one or more requested synchronization objects, selecting a subset of the candidate portions of the data structure and applying the operation only to the selected subset of the candidate portions.

    摘要翻译： 通常，本公开的技术涉及同步访问数据结构的多个部分。 在一个示例中，一种方法包括：从请求队列顺序地选择多个请求，其中至少一个请求为数据结构的相应候选部分指定多个请求的同步对象，以应用与 数据元素。 该方法还包括查询一个或多个标识符集合以确定由所选择的请求指定的所请求的同步对象中的一个或多个是可获取的。 该方法还包括获取可获取的所请求的同步对象中的每一个。 该方法包括：响应于获取所有一个或多个所请求的同步对象，选择数据结构的候选部分的子集，并将该操作仅应用于所选择的候选部分的子集。

    Flexible pin allocation
    28.
    发明授权
    Flexible pin allocation 有权
    灵活的引脚分配

    公开(公告)号：US08341584B1

    公开(公告)日：2012-12-25

    申请号：US12983024

    申请日：2010-12-31

    申请人： Srinivas Vaduvatha ,  Srinivas Venkataraman ,  Anurag P. Gupta ,  Praveen Garapally ,  Norman Bristol ,  Dibyendu Sen

    发明人： Srinivas Vaduvatha ,  Srinivas Venkataraman ,  Anurag P. Gupta ,  Praveen Garapally ,  Norman Bristol ,  Dibyendu Sen

    IPC分类号： G06F17/50

    CPC分类号： G06F12/00 ,  G06F13/409

    摘要： A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.

    摘要翻译： 系统包括存储器和控制器。 控制器可以包括一组焊盘和分配寄存器。 控制器被配置为接收对应于组的输入信号，并且基于存储器的引脚的配置来分配每个焊盘以输出输入信号之一。 控制器还被配置为基于焊盘的分配来重定向控制器内的输入信号，并将输入信号从控制器输出到焊盘中。