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公开(公告)号：US08427892B2
公开(公告)日：2013-04-23
申请号：US13156134
申请日：2011-06-08
IPC分类号： G11C7/00
CPC分类号： G06F13/1689 , Y02D10/14
摘要： A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.
摘要翻译： 存储器控制器包括产生用于对DDR SDRAM进行写操作的选通信号的电路。 该电路有效地为一组数据线产生无毛刺选通信号。 在一个实现中，存储器控制器包括一个写数据产生电路，每个数据产生电路在数据线上将数据信号发送到存储器，写数据产生电路由写使能信号控制。 写选通产生电路产生选通信号和写使能信号，选通信号包括用于发信号通知数据脉冲串的前导码窗口，数据传输窗口和后同步码窗口，用于发信号通知数据脉冲串的结束， 写选通产生电路提前将半存储器周期产生写使能信号，并将写使能信号相对于由写数据产生电路产生的数据信号延迟半个存储周期。
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2.发明申请公开(公告)号：US20110128793A1
公开(公告)日：2011-06-02
申请号：US13024448
申请日：2011-02-10
IPC分类号： G11C7/00
CPC分类号： G06F13/1689 , Y02D10/14
摘要： A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.
摘要翻译： 诸如用于读取从DDR SDRAM存储器接收的数据的存储器控制器的存储器控制器可以检测读周期的开始和结束。 存储器控制器可以包括前导码检测电路，用于接收选通信号并输出指示检测选通信号中的前导码窗口的第一控制信号，其指示读周期的开始，其中基于可选择的第一控制信号来延迟第一控制信号 延迟周期施加到第一控制信号。 存储器控制器还可以包括第一门，以便基于第一控制信号，输出选通信号以读取数据线或阻止选通信号，并且控制逻辑设置为可选延迟周期的量 前导码检测电路。
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公开(公告)号：US07113418B2
公开(公告)日：2006-09-26
申请号：US10700389
申请日：2003-11-04
CPC分类号： H05K1/181 , G11C5/00 , H05K2201/09709 , H05K2201/10159 , H05K2201/10545 , Y02P70/611
摘要： Memory systems and methods are described. In one embodiment, a circuit board has front and back surfaces. At least one memory device having a plurality of pins is mounted on the front surface of the circuit board. At least one other memory device having a plurality of pins is mounted on the back surface of the circuit board. The memory devices are mounted on the circuit board such that at least some pins from the one memory device align with at least some pins of the other memory device to provide aligned pin pairs. A via is disposed in the circuit board and extends between and connects individual pins of an aligned pin pair.
摘要翻译： 描述了内存系统和方法。 在一个实施例中，电路板具有正面和背面。 具有多个引脚的至少一个存储器件安装在电路板的前表面上。 具有多个引脚的至少一个其它存储器件安装在电路板的后表面上。 存储器件安装在电路板上，使得来自一个存储器件的至少一些引脚与另一个存储器件的至少一些引脚对准以提供对准的引脚对。 通孔设置在电路板中，并且在对准的销对的各个销之间延伸并连接。
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公开(公告)号：US08341584B1
公开(公告)日：2012-12-25
申请号：US12983024
申请日：2010-12-31
申请人： Srinivas Vaduvatha , Srinivas Venkataraman , Anurag P. Gupta , Praveen Garapally , Norman Bristol , Dibyendu Sen
发明人： Srinivas Vaduvatha , Srinivas Venkataraman , Anurag P. Gupta , Praveen Garapally , Norman Bristol , Dibyendu Sen
IPC分类号： G06F17/50
CPC分类号： G06F12/00 , G06F13/409
摘要： A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.
摘要翻译： 系统包括存储器和控制器。 控制器可以包括一组焊盘和分配寄存器。 控制器被配置为接收对应于组的输入信号，并且基于存储器的引脚的配置来分配每个焊盘以输出输入信号之一。 控制器还被配置为基于焊盘的分配来重定向控制器内的输入信号，并将输入信号从控制器输出到焊盘中。
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5.发明授权BGA footprint pattern for increasing number of routing channels per PCB layer 有权BGA占用空间图，每个PCB层增加路由通道数公开(公告)号：US08273994B2
公开(公告)日：2012-09-25
申请号：US12647737
申请日：2009-12-28
申请人： Boris Reynov , Ping Yue , Shreeram Siddhaye , John Cleveland , Chebrolu Srinivas , Srinivas Venkataraman
发明人： Boris Reynov , Ping Yue , Shreeram Siddhaye , John Cleveland , Chebrolu Srinivas , Srinivas Venkataraman
CPC分类号： H05K1/114 , H05K2201/09418 , H05K2201/097 , H05K2201/09709 , H05K2201/10734
摘要： A printed circuit board (PCB) includes a ball grid array (BGA). The PCB further includes a first BGA pad having a circular shape, and a first via having a circular shape, where the circular shape of the first via overlaps a portion of the circular shape of the first BGA pad and is rotated diagonally relative to a center of the first BGA pad. The PCB also includes a second BGA pad having a circular shape, and a second via having a circular shape, where the circular shape of the second via overlaps a portion of the circular shape of the second BGA pad and is rotated diagonally relative to a center of the second pad, and where a center of the second via is located at a first distance from the center of the first via and at a first angle relative to an axis that crosses a center of the first via.
摘要翻译： 印刷电路板（PCB）包括球栅阵列（BGA）。 PCB还包括具有圆形形状的第一BGA焊盘和具有圆形形状的第一通孔，其中第一通孔的圆形与第一BGA焊盘的圆形部分的一部分重叠并相对于中心对角地旋转 的第一个BGA垫。 PCB还包括具有圆形形状的第二BGA焊盘和具有圆形形状的第二通孔，其中第二通孔的圆形与第二BGA焊盘的圆形部分的一部分重叠并且相对于中心对角地旋转 并且其中第二通孔的中心位于距离第一通孔的中心的第一距离处，并且相对于穿过第一通孔的中心的轴线处于第一角度。
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公开(公告)号：US20110235446A1
公开(公告)日：2011-09-29
申请号：US13156134
申请日：2011-06-08
IPC分类号： G11C8/18
CPC分类号： G06F13/1689 , Y02D10/14
摘要： A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.
摘要翻译： 存储器控制器包括产生用于对DDR SDRAM进行写操作的选通信号的电路。 该电路有效地为一组数据线产生无毛刺选通信号。 在一个实现中，存储器控制器包括一个写数据产生电路，每个数据产生电路在数据线上将数据信号发送到存储器，写数据产生电路由写使能信号控制。 写选通产生电路产生选通信号和写使能信号，选通信号包括用于发信号通知数据脉冲串的前导码窗口，数据传输窗口和后同步码窗口，用于发信号通知数据脉冲串的结束， 写选通产生电路提前将半存储器周期产生写使能信号，并将写使能信号相对于由写数据产生电路产生的数据信号延迟半个存储周期。
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公开(公告)号：US20050097249A1
公开(公告)日：2005-05-05
申请号：US10700389
申请日：2003-11-04
CPC分类号： H05K1/181 , G11C5/00 , H05K2201/09709 , H05K2201/10159 , H05K2201/10545 , Y02P70/611
摘要： Memory systems and methods are described. In one embodiment, a circuit board has front and back surfaces. At least one memory device having a plurality of pins is mounted on the front surface of the circuit board. At least one other memory device having a plurality of pins is mounted on the back surface of the circuit board. The memory devices are mounted on the circuit board such that at least some pins from the one memory device align with at least some pins of the other memory device to provide aligned pin pairs. A via is disposed in the circuit board and extends between and connects individual pins of an aligned pin pair.
摘要翻译： 描述了内存系统和方法。 在一个实施例中，电路板具有正面和背面。 具有多个引脚的至少一个存储器件安装在电路板的前表面上。 具有多个引脚的至少一个其它存储器件安装在电路板的后表面上。 存储器件安装在电路板上，使得来自一个存储器件的至少一些引脚与另一个存储器件的至少一些引脚对准以提供对准的引脚对。 通孔设置在电路板中，并且在对准的销对的各个销之间延伸并连接。
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公开(公告)号：US08023342B2
公开(公告)日：2011-09-20
申请号：US13024448
申请日：2011-02-10
IPC分类号： G11C7/00
CPC分类号： G06F13/1689 , Y02D10/14
摘要： A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.
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公开(公告)号：US07990781B1
公开(公告)日：2011-08-02
申请号：US12489770
申请日：2009-06-23
IPC分类号： G11C7/00
CPC分类号： G06F13/1689 , Y02D10/14
摘要： A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.
摘要翻译： 存储器控制器包括产生用于对DDR SDRAM进行写操作的选通信号的电路。 该电路有效地为一组数据线产生无毛刺选通信号。 在一个实现中，存储器控制器包括一个写数据产生电路，每个数据产生电路在数据线上将数据信号发送到存储器，写数据产生电路由写使能信号控制。 写选通产生电路产生选通信号和写使能信号，选通信号包括用于发信号通知数据脉冲串的前导码窗口，数据传输窗口和后同步码窗口，用于发信号通知数据脉冲串的结束， 写选通产生电路提前将半存储器周期产生写使能信号，并将写使能信号相对于由写数据产生电路产生的数据信号延迟半个存储周期。
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10.发明授权Preamble detection and postamble closure for a memory interface controller 失效用于存储器接口控制器的前导码检测和后同步闭合公开(公告)号：US07911857B1
公开(公告)日：2011-03-22
申请号：US12482190
申请日：2009-06-10
IPC分类号： G11C7/00
CPC分类号： G06F13/1689 , Y02D10/14
摘要： A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.
摘要翻译： 诸如用于读取从DDR SDRAM存储器接收的数据的存储器控制器的存储器控制器可以检测读周期的开始和结束。 存储器控制器可以包括前导码检测电路，用于接收选通信号并输出指示检测选通信号中的前导码窗口的第一控制信号，其指示读周期的开始，其中基于可选择的第一控制信号来延迟第一控制信号 延迟周期施加到第一控制信号。 存储器控制器还可以包括第一门，以便基于第一控制信号，输出选通信号以读取数据线或阻止选通信号，并且控制逻辑设置为可选延迟周期的量 前导码检测电路。
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