公开(公告)号：US10942850B2

公开(公告)日：2021-03-09

申请号：US16513225

申请日：2019-07-16

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Aditya Venkataraman ,  Bryan R. Hinch ,  Daniel A. Chimene ,  Andrei Dorofeev ,  Constantin Pistol

IPC: G06F12/00 ,  G06F12/0802

Abstract: A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.

公开(公告)号：US10895903B2

公开(公告)日：2021-01-19

申请号：US16266248

申请日：2019-02-04

Applicant: Apple Inc.

Inventor： James S. Ismail ,  John M. Ananny ,  John G. Dorsey ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Keith Cox ,  Inder M. Sodhi ,  Achmed R. Zahir

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206 ,  G01R21/133

Abstract: In an embodiment, an electronic device includes a package power zone controller. The device monitors the overall power consumption of multiple components of a “package.” The package power zone controller may detect workloads in which the package components (e.g. different types of processors, peripheral hardware, etc.) are each consuming relatively low levels of power, but the overall power consumption is greater than a desired target. The package power zone controller may implement various mechanisms to reduce power consumption in such cases.

公开(公告)号：US20180349176A1

公开(公告)日：2018-12-06

申请号：US15870763

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

CPC classification number: G06F9/505 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/268 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4856 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/5044 ,  G06F9/5094 ,  G06F9/54 ,  G06F2209/501 ,  G06F2209/5018 ,  G06F2209/509

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.