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公开(公告)号：US11210104B1
公开(公告)日：2021-12-28
申请号：US17018963
申请日：2020-09-11
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Brian P. Lilly , James Vash , Jason M. Kassoff , Krishna C. Potnuru , Rajdeep L. Bhuyar , Ran A. Chachick , Tyler J. Huberty , Derek R. Kumar
Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.
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公开(公告)号：US20190155770A1
公开(公告)日：2019-05-23
申请号：US16195478
申请日：2018-11-19
Applicant: Apple Inc.
Inventor： Derek R. Kumar , Joshua Phillips de Cesare
IPC: G06F13/24 , G06F9/4401 , G06F1/3293
Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (WI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred WI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.
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公开(公告)号：US20190064893A1
公开(公告)日：2019-02-28
申请号：US16113397
申请日：2018-08-27
Applicant: Apple Inc.
Inventor： Derek R. Kumar
Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device manages a thermal profile of the device by adjusting a throttling a central processing unit execution of a historically high energy consuming task. In this embodiment, the device monitors thermal level of the thermal profile of the device, the device is executing a plurality of tasks that utilize a plurality of processing cores of the device. If the thermal level of the device exceeds a thermal threshold, the device identifies one of the plurality of tasks as a historically high energy consuming task, and throttles this historically high energy consuming task by setting a force idle execution time for the historically high energy consuming task. The device further executes the plurality of tasks.
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公开(公告)号：US09436628B2
公开(公告)日：2016-09-06
申请号：US14503312
申请日：2014-09-30
Applicant: Apple Inc.
Inventor： Umesh Suresh Vaishampayan , Derek R. Kumar , Christopher John Sarcone , Russell Alexader Blaine , Tejas Arun Bahulkar , Shachar Katz , Joseph Sokol, Jr. , Matthew John Byom
CPC classification number: G06F13/26 , G05D23/1917 , G06F1/206 , G06F13/102 , Y02D10/14 , Y02D10/16
Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling input/output operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilize storage of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first bandwidth range for the low priority process and maintains a second bandwidth range for the high priority process. The device further processes a storage request of the low priority process using the first bandwidth range and processing a storage request of the high priority process using the second bandwidth range.
Abstract translation: 描述了通过选择性地节流设备的输入/输出操作来管理设备的热轮廓的设备的方法和装置。 在示例性实施例中，设备监视设备的热分布，其中设备执行利用设备的存储的多个进程。 另外，多个处理包括高优先级处理和低优先级处理。 如果设备的热分布超过热阈值，则设备会降低低优先级进程的第一带宽范围，并为高优先级进程维护第二带宽范围。 该设备还使用第一带宽范围来处理低优先级进程的存储请求，并使用第二带宽范围来处理高优先级进程的存储请求。
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公开(公告)号：US20150346809A1
公开(公告)日：2015-12-03
申请号：US14503318
申请日：2014-09-30
Applicant: Apple Inc.
Inventor： Derek R. Kumar
IPC: G06F1/32
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3243 , G06F9/4893 , Y02D10/152 , Y02D10/16
Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device monitors the thermal profile of the device, where the device executes a plurality of tasks that utilizes a central processing unit of the device. In addition, the plurality of tasks includes a high QoS task and a low QoS process. If the thermal profile of the device exceeds a thermal threshold, the device increases a first CPU throttling for the low QoS task and maintains a second CPU throttling for the high QoS task. The device further executes the low QoS task using the first CPU utilization with the first processing core of the CPU by selectively forcing an idle of the low QoS task during an execution window. In addition, the device executes the high QoS task using the second CPU throttling with a second processing core of the CPU.
Abstract translation: 描述了通过选择性地节流设备的中央处理单元操作来管理设备的热分布的设备的方法和设备。 设备监视设备的热分布，其中设备执行利用设备的中央处理单元的多个任务。 另外，多个任务包括高QoS任务和低QoS进程。 如果设备的散热曲线超过热阈值，则设备会为低QoS任务增加第一个CPU限制，并维护高QoS任务的第二个CPU限制。 该设备还通过在执行窗口期间选择性地强制低QoS任务的空闲来执行使用与CPU的第一处理核心的第一CPU利用率的低QoS任务。 此外，设备使用CPU的第二个处理核心使用第二个CPU调节来执行高QoS任务。
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Patent Agency Ranking
公开(公告)号：US20220083343A1
公开(公告)日：2022-03-17
申请号：US17532072
申请日：2021-11-22
Applicant: Apple Inc.
Inventor： Aditya Kesiraju , Andrew J. Beaumont-Smith , Brian P. Lilly , James Vash , Jason M. Kassoff , Krishna C. Potnuru , Rajdeep L. Bhuyar , Ran A. Chachick , Tyler J. Huberty , Derek R. Kumar
Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.
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公开(公告)号：US10649935B2
公开(公告)日：2020-05-12
申请号：US16195478
申请日：2018-11-19
Applicant: Apple Inc.
Inventor： Derek R. Kumar , Joshua Phillips de Cesare
IPC: G06F13/24 , G06F1/3293 , G06F9/4401
Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.
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公开(公告)号：US10204058B2
公开(公告)日：2019-02-12
申请号：US15337526
申请日：2016-10-28
Applicant: Apple Inc.
Inventor： Derek R. Kumar
IPC: G06F12/1009 , G06F12/0804 , G06F12/1045
Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device manages a graphics processing unit working set of pages. In this embodiment, the device determines the set of pages of the device to be analyzed, where the device includes a central processing unit and the graphics processing unit. The device additionally classifies the set of pages based on a graphics processing unit activity associated with the set of pages and evicts a page of the set of pages based on the classifying.
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公开(公告)号：US20170357454A1
公开(公告)日：2017-12-14
申请号：US15491740
申请日：2017-04-19
Applicant: Apple Inc.
Inventor： Derek R. Kumar , Thomas Brogan Duffy, JR.
IPC: G06F3/06
CPC classification number: H03M7/30 , H03M7/46 , H03M7/6094
Abstract: A method and apparatus of a device that compresses an object stored in memory is described. In an exemplary embodiment, the device receives an indication that the object is to be compressed. The device further selects one of a plurality of compression algorithms based on at least a characteristic of the object. In addition, the device compresses the object in-memory using the selected compression algorithm.
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30.发明授权Intelligent GPU memory pre-fetching and GPU translation lookaside buffer management 有权智能GPU内存预取和GPU翻译后备缓存管理公开(公告)号：US09563571B2
公开(公告)日：2017-02-07
申请号：US14262500
申请日：2014-04-25
Applicant: Apple Inc.
Inventor： Derek R. Kumar
CPC classification number: G06F12/1027 , G06F12/1009 , G06F2212/654 , G06F2212/657
Abstract: A method and apparatus of a device that manages virtual memory for a graphics processing unit is described. In an exemplary embodiment, the device performs translation lookaside buffer coherency for a translation lookaside buffer of the graphics processing unit of the device. In this embodiment, the device receives a request to remove an entry of the translation lookaside buffer of the graphics processing unit, where the device includes a central processing unit and the graphics processing unit. In addition, the entry includes a translation of virtual memory address of a process to a physical memory address of system memory of a central processing unit and the graphics processing unit is executing a compute task of the process. The device locates the entry in the translation lookaside buffer and removes the entry.
Abstract translation: 描述了管理图形处理单元的虚拟存储器的设备的方法和装置。 在示例性实施例中，设备为设备的图形处理单元的翻译后备缓冲器执行翻译后备缓冲器一致性。 在本实施例中，设备接收去除图形处理单元的翻译后备缓冲器的条目的请求，其中该设备包括中央处理单元和图形处理单元。 此外，条目包括将进程的虚拟内存地址转换为中央处理单元的系统存储器的物理存储器地址，并且图形处理单元正在执行该进程的计算任务。 设备将条目定位在翻译后备缓冲区中，并删除条目。
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