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公开(公告)号：US11467655B1
公开(公告)日：2022-10-11
申请号：US17340940
申请日：2021-06-07
Applicant: Apple Inc.
Inventor： Inder M. Sodhi , Achmed R. Zahir , Lior Zimet , Liran Fishel , Omri Flint , Ami Schwartzman
IPC: G06F1/00 , G06F1/3296 , G06F1/3206
Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.
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公开(公告)号：US20220300749A1
公开(公告)日：2022-09-22
申请号：US17206901
申请日：2021-03-19
Applicant: Apple Inc.
Inventor： Liran Fishel , Assaf Metuki , Chuhan Min , Wai Yu Trevor Tsang
Abstract: Embodiments relate to generating keypoint descriptors of the keypoints. An apparatus includes a pyramid image generator circuit and a keypoint descriptor generator circuit. The pyramid image generator circuit generates an image pyramid from an input image. The keypoint descriptor generator circuit determines intensity values of sample points in the pyramid images for a keypoint and determines comparison results of comparisons between the intensity values of pairs of the sample points. The keypoint descriptor generator circuit generate bit values defining the comparison results for the keypoint, each bit value corresponding with one of the comparison results, and generate a sequence of the bit values defining an ordering of the comparison results based on importance levels of the comparisons, where the importance level of each comparison defines how much the comparison is representative of features. Bit values for comparisons having the lowest importance levels may be excluded from the sequence.
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公开(公告)号：US20220019875A1
公开(公告)日：2022-01-20
申请号：US17473454
申请日：2021-09-13
Applicant: Apple Inc.
Inventor： Liran Fishel , Sung Hee Park , Christopher L. Mills
IPC: G06N3/04
Abstract: Embodiments relate to a neural processor circuit that includes a kernel access circuit and multiple neural engine circuits. The kernel access circuit reads compressed kernel data from memory external to the neural processor circuit. Each neural engine circuit receives compressed kernel data from the kernel access circuit. Each neural engine circuit includes a kernel extract circuit and a kernel multiply-add (MAD) circuit. The kernel extract circuit extracts uncompressed kernel data from the compressed kernel data. The kernel MAD circuit receives the uncompressed kernel data from the kernel extract circuit and performs neural network operations on a portion of input data using the uncompressed kernel data.
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公开(公告)号：US20190340014A1
公开(公告)日：2019-11-07
申请号：US15971276
申请日：2018-05-04
Applicant: Apple Inc.
Inventor： Liran Fishel , Erik K. Norden
Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. A neural task manager circuit within the neural processor circuit can switch between tasks in different task queues. Each task queue is configured to store a reference to a task list of tasks for instantiating a neural network. Each task queue can also be assigned a priority parameter. While the neural processor circuit is executing tasks of a first task list and prior to completion of each task, the neural task manager circuit can switch between task queues according to the priority parameters for execution of tasks of a second task list by the neural processor circuit. The neural processor circuit includes one or more neural engine circuits that are configured to perform neural operations by executing the tasks assigned by the task manager.
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公开(公告)号：US20240265233A1
公开(公告)日：2024-08-08
申请号：US18614256
申请日：2024-03-22
Applicant: Apple Inc.
Inventor： Erik Norden , Liran Fishel , Sung Hee Park , Jaewon Shin , Christopher L. Mills , Seungjin Lee , Fernando A. Mujica
IPC: G06N3/04 , G06F1/3296 , G06N3/08
CPC classification number: G06N3/04 , G06F1/3296 , G06N3/08
Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.
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Patent Agency Ranking
公开(公告)号：US11968471B2
公开(公告)日：2024-04-23
申请号：US17195520
申请日：2021-03-08
Applicant: Apple Inc.
Inventor： David R. Pope , Liran Fishel , Assaf Metuki , Muge Wang
CPC classification number: H04N5/76 , G06T1/60 , G06T7/251 , H04N1/2141 , G06T2207/20016
Abstract: Embodiments relate to extracting features from images, such as by identifying keypoints and generating keypoint descriptors of the keypoints. An apparatus includes a pyramid image generator circuit, a keypoint descriptor generator circuit, and a pyramid image buffer. The pyramid image generator circuit generates an image pyramid from an input image. The keypoint descriptor generator circuit processes the pyramid images for keypoint descriptor generation. The pyramid image buffer stores different portions of the pyramid images generated by the pyramid image generator circuit at different times and provides the stored portions of the pyramid images to the keypoint descriptor generator circuit for keypoint descriptor generation. When first portions of the pyramid images are no longer needed for the keypoint descriptor generation, the first portions are removed from the pyramid image buffer to provide space for second portions of the pyramid images that are needed for the keypoint descriptor generation.
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27.发明授权公开(公告)号：US11914500B2
公开(公告)日：2024-02-27
申请号：US17591888
申请日：2022-02-03
Applicant: Apple Inc.
Inventor： Liran Fishel , Danny Gal , Nir Nissan
CPC classification number: G06F11/3636 , G06F9/3004 , G06F9/30036 , G06F9/30145 , G06F9/321 , G06F11/3656
Abstract: Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.
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公开(公告)号：US11899523B2
公开(公告)日：2024-02-13
申请号：US17933168
申请日：2022-09-19
Applicant: Apple Inc.
Inventor： Inder M. Sodhi , Achmed R. Zahir , Lior Zimet , Liran Fishel , Omri Flint , Ami Schwartzman
IPC: G06F1/00 , G06F1/3296 , G06F1/3206
CPC classification number: G06F1/3296 , G06F1/3206
Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.
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公开(公告)号：US20230316706A1
公开(公告)日：2023-10-05
申请号：US17693007
申请日：2022-03-11
Applicant: Apple Inc.
Inventor： Assaf Metuki , Lukas Polok , Danny Gal , Liran Fishel
CPC classification number: G06V10/757 , G06V10/761
Abstract: Embodiments of the present disclosure relate to selecting a subset of keypoint descriptors of two images for match operation based on their orientation angles indicated in headers of the keypoint descriptors. The keypoint descriptors in the two images are matched by first comparing their headers and then performing vector distance determination. During the header comparison operation, a header of a descriptor of a first image is compared only with headers of keypoint descriptors of a second image in a discrete orientation angle range corresponding to an orientation angle indicated by the header of the first image descriptor or keypoint descriptors of the second image in adjacent discrete orientation angle ranges. After the headers of the keypoint descriptors satisfying one or more matching criteria are determined, distance determination operations are performed between the keypoint descriptors while the remaining keypoint descriptors are discarded without determining their distances.
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30.发明公开公开(公告)号：US20230281106A1
公开(公告)日：2023-09-07
申请号：US17591888
申请日：2022-02-03
Applicant: Apple Inc.
Inventor： Liran Fishel , Danny Gal , Nir Nissan
CPC classification number: G06F11/3636 , G06F9/30036 , G06F9/3004 , G06F9/30145 , G06F9/321 , G06F11/3656
Abstract: Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.
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