公开(公告)号：US12027607B2

公开(公告)日：2024-07-02

申请号：US17843968

申请日：2022-06-18

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Matthias Bauer ,  Naved Ahmed Siddiqui ,  Phillip Stout

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/78696

Abstract: Electronic devices and methods of forming electronic devices with gate-all-around non-I/O devices and finlike structures for I/O devices are described. A plurality of dummy gates is etched to expose a fin comprising alternating layers of a first material and a second material. The second material layers are removed to create openings and the first material layers remaining are epitaxially grown to form a finlike structure.

公开(公告)号：US20230299199A1

公开(公告)日：2023-09-21

申请号：US18324711

申请日：2023-05-26

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Mehdi Saremi ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/78

CPC classification number: H01L29/7842

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

公开(公告)号：US20230260909A1

公开(公告)日：2023-08-17

申请号：US18106643

申请日：2023-02-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Yeoh ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Ashish Pal

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/401 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.

公开(公告)号：US20230260908A1

公开(公告)日：2023-08-17

申请号：US18106621

申请日：2023-02-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Yeoh ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Ashish Pal ,  El Mehdi Bazizi

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02532 ,  H01L29/401 ,  H01L29/66553 ,  H01L29/66439

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.

公开(公告)号：US11699755B2

公开(公告)日：2023-07-11

申请号：US17000546

申请日：2020-08-24

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Mehdi Saremi ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/78

CPC classification number: H01L29/7842

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

公开(公告)号：US20230040606A1

公开(公告)日：2023-02-09

申请号：US17879088

申请日：2022-08-02

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Saurabh Chopra ,  Myungsun Kim ,  Balasubramanian Pranatharthiharan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

公开(公告)号：US20230014586A1

公开(公告)日：2023-01-19

申请号：US17956061

申请日：2022-09-29

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Hans-Joachim Gossmann

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L21/324 ,  H01L21/02

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US11271097B2

公开(公告)日：2022-03-08

申请号：US17080519

申请日：2020-10-26

Applicant: Applied Materials, Inc.

Inventor： Steven C. Hung ,  Benjamin Colombeau ,  Abhishek Dube ,  Sheng-Chin Kung ,  Patricia M. Liu ,  Malcolm J. Bevan ,  Johanes Swenberg

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.

公开(公告)号：US20220037529A1

公开(公告)日：2022-02-03

申请号：US17386711

申请日：2021-07-28

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Michael Stolfi ,  Benjamin Colombeau ,  Andy Lo

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/15 ,  H01L21/8234 ,  H01L21/02

Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US20210193468A1

公开(公告)日：2021-06-24

申请号：US17192213

申请日：2021-03-04

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Lin Dong ,  Benjamin Colombeau ,  Johanes F. Swenberg ,  Linlin Wang

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/02

Abstract: A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-κ dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-κ dielectric layer.