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公开(公告)号：US20180232935A1
公开(公告)日：2018-08-16
申请号：US15433398
申请日：2017-02-15
Applicant: ARM Limited
Inventor： Alexander Galazin , Jörg Wagner , Andreas Due Engh-Halstvedt
CPC classification number: G06T15/005 , G06F9/44 , G06T15/80
Abstract: A graphics processing system groups plural initial pilot shader programs into a set of initial pilot shader programs and associates the set of initial pilot shader programs with a set of indexes. The initial pilot shader programs each contain constant program expressions to be executed on behalf of an original shader program. The index for an initial pilot shader program is then used to obtain the instructions contained in the initial pilot shader program for executing the constant program expressions of the initial pilot shader program. The threads for executing a subset of the initial pilot shader programs are also grouped into a thread group and the threads of the thread group are executed in parallel. The graphics processing system provides for efficient preparation and execution of plural initial pilot shader programs.
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公开(公告)号：US09933999B2
公开(公告)日：2018-04-03
申请号：US14878562
申请日：2015-10-08
Applicant: ARM Limited
Inventor： Andreas Due Engh-Halstvedt , Edvard Fielding
CPC classification number: G06F7/506 , G06F7/5272 , G06F7/535 , H03M7/24
Abstract: An apparatus, method and program are provided for calculating a result value to a required precision of a repeating iterative sum, wherein the repeating iterative sum comprises multiple iterations of an addition using an input value. Addition is performed in a single iteration of addition as a sum operation using overlapping portions of the input value and a shifted version of the input value, wherein the shifted version of the input value has a partial overlap with the input value. At least one result portion is produced by incrementing an input derived from the input value using the output from the sum operation and the result value is constructed using the at least one result portion to give the result value to the required precision. The repeating iterative sum is thereby flattened into a flattened calculation which requires only a single iteration of addition using the input value, thus facilitating the calculation of the result value of the repeating iterative sum.
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公开(公告)号：US20170193691A1
公开(公告)日：2017-07-06
申请号：US15393120
申请日：2016-12-28
Applicant: ARM Limited
Inventor： Frank Langtind , Andreas Due Engh-Halstvedt , Sandeep Kakarlapudi
CPC classification number: G06T15/80 , G06F9/3879 , G06T1/20 , G06T15/005 , G06T17/20 , G09G5/363
Abstract: A graphics processing pipeline includes position shading circuitry, a tiler, varying-only vertex shading circuitry and fragment (frontend) shading circuitry. The tiler reads a list of indices defining a set of vertices to be processed by the graphics processing pipeline and determines whether or not vertex shading is required for the positional attributes of the vertices. If vertex shading is required, the tiler sends a position shading request for the vertices to the position shading circuitry. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output and that accordingly should be subjected to a second, varying shading, vertex shading operation. When the tiler determines that a vertex (or group of vertices) should be subjected to the second, varying shading, vertex shading operation, the tiler sends a varying shading request for the vertex (or vertices) to the varying shading circuitry.
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公开(公告)号：US20160247249A1
公开(公告)日：2016-08-25
申请号：US15049392
申请日：2016-02-22
Applicant: ARM Limited
CPC classification number: G06T9/00 , G06T11/40 , G06T15/005
Abstract: A graphics processing pipeline includes processing circuitry. The processing circuitry is configured to determine attribute information for an object to be rendered for a set of sampling points from a compressed representation of attribute information associated with the object, when the set of sampling points is being processed by the graphics processing pipeline to generate a render output. The processing circuitry is also configured to use the determined attribute information to control the processing of the set of sampling points by the graphics processing pipeline when generating the render output.
Abstract translation: 图形处理流水线包括处理电路。 所述处理电路被配置为当所述采样点集合被所述图形处理流水线处理以产生一个或多个采样点时，从与所述对象相关联的属性信息的压缩表示中，为一组采样点确定要渲染的对象的属性信息 渲染输出。 处理电路还被配置为使用所确定的属性信息来在生成渲染输出时由图形处理流水线控制该组采样点的处理。
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公开(公告)号：US11734869B2
公开(公告)日：2023-08-22
申请号：US17511032
申请日：2021-10-26
Applicant: Arm Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Klaeboe Langtind , Mark Underwood
CPC classification number: G06T15/005 , G06T1/20 , G06T1/60 , G06T15/80
Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.
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Patent Agency Ranking
公开(公告)号：US11625332B2
公开(公告)日：2023-04-11
申请号：US16742519
申请日：2020-01-14
Applicant: Arm Limited
Inventor： Olof Henrik Uhrenholt , Andreas Due Engh-Halstvedt
IPC: G06F12/0891 , G06F12/0893 , G06F9/54 , G06F12/02 , G06F9/30 , G06F12/0811
Abstract: In a data processing system comprising a cache system configured to transfer data stored in a memory system to a processor and vice-versa, a processing unit operable to read data from a cache of the cache system can send a read request for data to the cache. The cache system, in response to the read request, determines whether the requested data is present in the cache. When the requested data is present in the cache, the cache system returns the data from the cache to the processing unit and invalidates the entry for the data in the cache. When the requested data is not present in the cache, the cache system returns an indication of that to the processing unit, without the cache system sending a request for the data towards the memory system.
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公开(公告)号：US20220308884A1
公开(公告)日：2022-09-29
申请号：US17656346
申请日：2022-03-24
Applicant: Arm Limited
IPC: G06F9/38
Abstract: A data processor comprising an execution engine 51 for executing programs for execution threads and one or more caches 48, 49 operable to store data values for use when executing program instructions to perform processing operations for execution threads. The data processor further comprises a thread throttling control unit 54 configured to monitor the operation of the caches 48, 49 during execution of programs for execution threads, and to control the issuing of instructions for execution threads to the execution engine for executing a program based on the monitoring of the operation of the caches during execution of the program.
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公开(公告)号：US20220245751A1
公开(公告)日：2022-08-04
申请号：US17163289
申请日：2021-01-29
Applicant: Arm Limited
Inventor： Frank Klaeboe Langtind , Andreas Due Engh-Halstvedt
Abstract: When generating a graphics processing output, a sequence of one or more of primitives to be processed when generating the output is assembled from a set of vertex indices provided for the output based on primitive configuration information provided for the output, each assembled primitive of the sequence of assembled primitives comprising an identifier for the primitive and a set of one or more vertex indices for the primitive. One or more attributes for vertices of the assembled primitives are then shaded and fetched based on the vertex indices of the assembled primitives. The assembled primitives including their shaded fetched vertex attribute(s) are then provided to later stages of the graphics processing pipeline for processing.
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公开(公告)号：US11205243B2
公开(公告)日：2021-12-21
申请号：US16742556
申请日：2020-01-14
Applicant: Arm Limited
Inventor： Olof Henrik Uhrenholt , Andreas Due Engh-Halstvedt
IPC: G06T9/00 , G06T1/60 , G06F12/0875 , G06T1/20
Abstract: A data processing system includes a memory and a processor in communication with the memory. The processor is configured to, when storing an array of data in the memory, produce information representative of the content of a block of data representing a particular region of the array of data, write the block of data to a data structure in the memory, and write the information representative of the content of the block of data to the data structure.
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公开(公告)号：US11170555B2
公开(公告)日：2021-11-09
申请号：US16697984
申请日：2019-11-27
Applicant: Arm Limited
Inventor： Ian Rudolf Bratt , Andreas Due Engh-Halstvedt , Alexander Eugene Chalfin , Andreas Loeve Selvik , Olof Henrik Uhrenholt , Thomas J. Olson
Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions (40) for rendering, each region (40) comprising a respective area of the render output; and for sets of one or more primitives to be rendered, it is determined for which of the plurality of regions of the render output (40) the primitive(s) should be rendered; and for each region of the render output (40) it is determined the primitive(s) should be rendered for, geometry data for the primitive(s) is stored in memory in a respective data structure (42) along with an indication of state data that is to be used for rendering the primitive(s) for the region, such that the geometry data for the primitive(s) to be rendered is stored in a respective, different data structure (42) for each different region of the render output (40) it is determined the primitive(s) should be rendered for.
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