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    Digital sampling techniques
    22.
    发明授权
    Digital sampling techniques 有权

    公开(公告)号：US11569824B2

    公开(公告)日：2023-01-31

    申请号：US17344390

    申请日：2021-06-10

    Applicant: Arm Limited

    Inventor： Shidhartha Das ,  Yunpeng Cai ,  Supreet Jeloka

    IPC: H03L7/099 ,  H03L7/187 ,  H03L7/091 ,  H03L7/199 ,  H03L7/081

    Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

    Memory for Artificial Neural Network Accelerator
    23.
    发明申请
    Memory for Artificial Neural Network Accelerator 有权

    公开(公告)号：US20220351032A1

    公开(公告)日：2022-11-03

    申请号：US17242721

    申请日：2021-04-28

    Applicant: Arm Limited

    Inventor： Teyuh Alice Chou ,  Mudit Bhargava ,  Supreet Jeloka ,  Fernando Garcia Redondo ,  Paul Nicholas Whatmough

    IPC: G06N3/063 ,  G06F17/16

    Abstract: A compute-in-memory (CIM) array module and a method for performing dynamic saturation detection for a CIM array are provided. The CIM array module includes a CIM array, saturation detection units (SDUs) and a controller. The CIM array includes selectable row signal lines, column signal lines and cells. Each cell is located at an intersection of a selectable row signal line and a column signal line, and each cell has a programmable conductance. The SDUs are selectively coupled to at least one column signal line, and each SDU is configured to, for each column signal line, generate an analog signal, and identify the column signal line as a saturated column signal line when a voltage of the analog signal is greater than a saturation threshold voltage, or a current of the analog signal is greater than a saturation threshold current.

    MEMORY DEVICE WITH ON-CHIP SACRIFICIAL MEMORY CELLS
    24.
    发明申请
    MEMORY DEVICE WITH ON-CHIP SACRIFICIAL MEMORY CELLS 有权

    公开(公告)号：US20220208265A1

    公开(公告)日：2022-06-30

    申请号：US17139059

    申请日：2020-12-31

    Applicant: Arm Limited

    Inventor： Fernando Garcia Redondo ,  Mudit Bhargava ,  Pranay Prabhat ,  Supreet Jeloka

    IPC: G11C13/00 ,  G11C11/16

    Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

    Memory for an Artificial Neural Network Accelerator
    26.
    发明申请
    Memory for an Artificial Neural Network Accelerator 有权

    公开(公告)号：US20220164137A1

    公开(公告)日：2022-05-26

    申请号：US17103629

    申请日：2020-11-24

    Applicant: Arm Limited

    Inventor： Mudit Bhargava ,  Paul Nicholas Whatmough ,  Supreet Jeloka ,  Zhi-Gang Liu

    IPC: G06F3/06 ,  G06N3/063

    Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of read word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each read word selector has a plurality of input ports and an output port, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the read word selectors of the first bank and the second bank, and configured to select a combination of read word selectors from at least one of the first bank and the second bank based on a bank select signal.

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