METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP

    公开(公告)号:US20220395254A1

    公开(公告)日:2022-12-15

    申请号:US17853835

    申请日:2022-06-29

    Abstract: Aspects of the disclosure described herein related to packaging an ultrasound-on-a-chip. In some embodiments, an apparatus includes an ultrasound-on-a-chip that has through-silicon vias (TSVs) and an interposer coupled to the ultrasound-on-a-chip and including vias, where the ultrasound-on-a-chip is coupled to the interposer such that the TSVs in the ultrasound-on-a-chip are electrically connected to the vias in the interposer. In some embodiments, an apparatus includes an ultrasound-on-a-chip having bond pads, an interposer that has bond pads and that is coupled to the ultrasound-on-a-chip, and wirebonds extending from the bond pads on the ultrasound-on-a-chip to the bond pads on the interposer.

    ADAPTIVE CAVITY THICKNESS CONTROL FOR MICROMACHINED ULTRASONIC TRANSDUCER DEVICES

    公开(公告)号:US20240416385A1

    公开(公告)日:2024-12-19

    申请号:US18813377

    申请日:2024-08-23

    Abstract: A method of forming an ultrasonic transducer device includes forming and patterning a film stack over a substrate, the film stack comprising a metal electrode layer and a chemical mechanical polishing (CMP) stop layer formed over the metal electrode layer; forming an insulation layer over the patterned film stack; planarizing the insulation layer to the CMP stop layer; measuring a remaining thickness of the CMP stop layer; and forming a membrane support layer over the patterned film stack, wherein the membrane support layer is formed at thickness dependent upon the measured remaining thickness of the CMP stop layer, such that a combined thickness of the CMP stop layer and the membrane support layer corresponds to a desired transducer cavity depth.

    Ultrasound devices
    23.
    发明授权

    公开(公告)号:US11986349B2

    公开(公告)日:2024-05-21

    申请号:US16401630

    申请日:2019-05-02

    Abstract: An ultrasound device is described. The ultrasound device may include a cavity, a membrane, and a sensing electrode. When an electrical signal is applied to the sensing electrode and a static bias is applied to the membrane, the membrane vibrates within the cavity and produces ultrasonic signals. The cavity, the membrane, and the sensing electrode may be considered a capacitive micromachined ultrasonic transducer (CMUT). The sensing electrode may be shaped as a ring, whereby the central portion of the sensing electrode is removed. Removal of the central portion of the sensing electrode may reduce the parasitic capacitance without substantially affecting the production of ultrasonic signals by the CMUT. This, in turn, can result in an increase in the signal-to-noise ratio (SNR) of the ultrasonic signals. The ultrasound device may further include a bond pad configured for wire bonding, and a trench electrically isolating the bond pad from the membrane.

    PACKAGING STRUCTURES AND PACKAGING METHODS FOR ULTRASOUND-ON-CHIP DEVICES

    公开(公告)号:US20230034707A1

    公开(公告)日:2023-02-02

    申请号:US17962408

    申请日:2022-10-07

    Abstract: A method of manufacturing an ultrasound imaging device involves forming an interposer structure, including forming a first metal material within openings through a substate and on top and bottom surfaces of the substrate, patterning the first metal material, forming a dielectric layer over the patterned first metal material, forming openings within the dielectric layer to expose portions of the patterned first metal material, filling the openings with a second metal material, forming a third metal material on the top and bottom surfaces of the substrate, and patterning the third metal material. The method further involves forming a packaging structure for an ultrasound-on-chip device, including attaching a multi-layer flex substrate to a carrier wafer, bonding a first side of an ultrasound-on-chip device to the multi-layer flex substrate, bonding a second side of the ultrasound-on-chip device to a first side of the interposer structure, and removing the carrier wafer.

    Bottom electrode via structures for micromachined ultrasonic transducer devices

    公开(公告)号:US11484911B2

    公开(公告)日:2022-11-01

    申请号:US16844857

    申请日:2020-04-09

    Abstract: A ultrasonic transducer device includes a transducer bottom electrode layer disposed over a substrate, and a plurality of vias that electrically connect the bottom electrode layer with the substrate, wherein substantially an entirety of the plurality of vias are disposed directly below a footprint of a transducer cavity. Alternatively, the transducer bottom electrode layer includes a first metal layer in contact with the plurality of vias and a second metal layer formed on the first metal layer, the first metal layer including a same material as the plurality of vias.

    Vertical packaging for ultrasound-on-a-chip and related methods

    公开(公告)号:US11426143B2

    公开(公告)日:2022-08-30

    申请号:US17088336

    申请日:2020-11-03

    Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

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