公开(公告)号：US20210193013A1

公开(公告)日：2021-06-24

申请号：US16945110

申请日：2020-07-31

Applicant: Beijing BOE Technology Development Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Chen XU ,  Xueguang Hao ,  Yong Qiao ,  Xinyin Wu

IPC: G09G3/20 ,  G09G3/3275 ,  G09G3/3266 ,  G09G3/3233 ,  H01L27/32

Abstract: Disclosed are an array substrate, a display panel and a display device. The display panel includes a plurality of sub-pixel regions; each of the sub-pixel regions includes a pixel driving circuit, a white electroluminescent device connected with the pixel driving circuit and a color resist layer corresponding to the sub-pixel region; the plurality of sub-pixel regions include a first-color sub-pixel region, a second-color sub-pixel region and a third-color sub-pixel region; a width-to-length ratio of a channel region of the driving transistor in the first-color sub-pixel region is greater than a width-to-length ratio of a channel region of the driving transistor in the second-color sub-pixel region, and the width-to-length ratio of the channel region of the driving transistor in the second-color sub-pixel region is greater than a width-to-length ratio of a channel region of the driving transistor in the third-color sub-pixel region.

公开(公告)号：US20170194416A1

公开(公告)日：2017-07-06

申请号：US15321151

申请日：2016-03-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liqiang CHEN ,  Tao GAO ,  Jing GAO ,  Chen XU

IPC: H01L27/32 ,  H01L51/52 ,  H01L51/56

Abstract: The present disclosure relates to the field of display technology, and provides an array substrate, its manufacturing method and a display device. The array substrate includes a display region and a GOA circuit region arranged outside the display region. A PMOLED display array is formed at the GOA circuit region.

公开(公告)号：US20250113610A1

公开(公告)日：2025-04-03

申请号：US18292106

申请日：2022-09-28

Applicant: Chongqing BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Bin WAN ,  Xiaoyuan WANG ,  Hui GUO ,  Chen XU ,  Jiandong GUO ,  Zhongshan WU ,  Guodong YANG ,  Junming CHEN ,  Yan LIU

IPC: H10D86/40 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

Abstract: A display substrate, including: a first base substrate, including a display region and a peripheral region surrounding the display region; at least one common voltage line in the display region, each being configured with at least one conductive connection region; a first passivation layer on a side of the common voltage line away from the first base substrate; a common electrode on a side of the first passivation layer away from the first base substrate; a second passivation layer on a side of the common electrode away from the first base substrate; a pixel electrode on a side of the second passivation layer away from the first base substrate; and a first conductive connection electrode in the corresponding conductive connection region and in the same layer as the pixel electrode, where the common electrode is electrically connected to the common voltage line through the first conductive connection electrode.

公开(公告)号：US20240304684A1

公开(公告)日：2024-09-12

申请号：US18028221

申请日：2022-03-28

Applicant: Hefei Xinsheng Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Ming WANG ,  Liusong NI ,  Kangkang WU ,  Yingbin HU ,  Chen XU

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/66969 ,  H01L29/7869

Abstract: Disclosed are a thin film transistor and preparation method thereof, display substrate and display apparatus. The thin film transistor includes a base substrate, a shielding layer, buffer layer, active layer, gate insulating layer and conductive layer stacked on the base substrate; the conductive layer includes a gate electrode, source electrode and drain electrode; the active layer includes a channel region, source transition region and drain transition region at two sides of the channel region, source connection region and drain connection region; the source transition region and drain transition region each include a first sub-region, second sub-region and third sub-region connected sequentially, first sub-region is located on a side of second sub-region away from the channel region, third sub-region is located on a side of second sub-region close to the channel region, a thickness of second sub-region is k times that of the channel region, k is 0.8 to 1.5.

公开(公告)号：US20240298461A1

公开(公告)日：2024-09-05

申请号：US18663458

申请日：2024-05-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xinwei GAO ,  Kaihong MA ,  Dacheng ZHANG ,  Lang LIU ,  Chen XU

IPC: H10K50/844 ,  H10K50/842 ,  H10K59/12 ,  H10K59/131 ,  H10K71/00

CPC classification number: H10K50/844 ,  H10K50/8426 ,  H10K59/131 ,  H10K71/00 ,  H10K59/1201

Abstract: A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel has a display region and a border region that surrounds the display region and includes a peripheral circuit region and a peripheral region; the peripheral circuit region is between the display region and the peripheral region. At least a part of a barrier structure of the display panel is in the peripheral circuit region, and the barrier structure includes an organic barrier layer including an opening passing through the organic barrier layer and an inorganic barrier layer covering the organic barrier layer and filling the opening; an extension direction of the opening is same as that of an edge, close to the opening, of the display panel; the peripheral circuit is in the peripheral circuit region.

公开(公告)号：US20220399523A1

公开(公告)日：2022-12-15

申请号：US16977285

申请日：2019-10-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xinwei GAO ,  Kaihong MA ,  Dacheng ZHANG ,  Lang LIU ,  Chen XU

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/56

Abstract: A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel has a display region and a border region that surrounds the display region and includes a peripheral circuit region and a peripheral region; the peripheral circuit region is between the display region and the peripheral region. At least a part of a barrier structure of the display panel is in the peripheral circuit region, and the barrier structure includes an organic barrier layer including an opening passing through the organic barrier layer and an inorganic barrier layer covering the organic barrier layer and filling the opening; an extension direction of the opening is same as that of an edge, close to the opening, of the display panel the peripheral circuit is in the peripheral circuit region.

公开(公告)号：US20220376014A1

公开(公告)日：2022-11-24

申请号：US16958890

申请日：2019-08-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Dachao LI ,  Shengji YANG ,  Chen XU

IPC: H01L27/32 ,  G09G3/3233 ,  H01L51/56

Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate, and the pixel circuit includes a driving transistor, a first transistor, and a second transistor; the driving transistor includes a control electrode, a first electrode, and a second electrode; the first transistor includes a first active region, the second transistor includes a second active region, the driving transistor includes a fourth active region, at least one of a doping concentration of the first active region and a doping concentration of the second active region is greater than a doping concentration of the fourth active region.

公开(公告)号：US20220151090A1

公开(公告)日：2022-05-12

申请号：US17297130

申请日：2020-06-24

Applicant: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yongda MA ,  Jianbo XIAN ,  Xueguang HAO ,  Chen XU

IPC: H05K5/02 ,  H05K5/00 ,  H05K5/03

Abstract: A display device includes: a display panel; a housing configured to support and protect the display panel; a bracket disposed between the display panel and the housing; a plurality of sensors fixed on the bracket; a window located in the display panel or in the housing, and configured to expose at least one of the plurality of sensors; and a driver configured to control the bracket to rotate in a plane parallel to the display panel, and to control the bracket to stop rotating when a required sensor rotates to a position of the window.

公开(公告)号：US20210366379A1

公开(公告)日：2021-11-25

申请号：US17255502

申请日：2019-12-13

Applicant: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chen XU ,  Xueguang HAO ,  Yong QIAO ,  Xinyin WU

IPC: G09G3/3225 ,  G09G3/3266 ,  H01L27/32

Abstract: The present disclosure provides a display substrate, in which power lines and compensation detection lines are alternately arranged at intervals, and two columns of pixel driving circuits extending along a second direction are arranged between any one of the power lines and one adjacent compensation detection line; and for any one of a plurality of pixel driving circuits, a power input terminal of the pixel driving circuit is electrically connected to the power line closest to the pixel driving circuit, and a compensation detection signal terminal of the pixel driving circuit is electrically connected to the compensation detection line closest to the pixel driving circuit. The present disclosure further provides a display device.

公开(公告)号：US20210151435A1

公开(公告)日：2021-05-20

申请号：US16642723

申请日：2019-03-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhi WANG ,  Feng GUAN ,  Guangcai YUAN ,  Chen XU ,  Lei CHEN

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238

Abstract: The disclosure relates to a CMOS structure and a manufacturing method thereof. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer therebetween. The first active layer includes a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. An N-type doping concentration of the second semiconductor layer is smaller than that of the third semiconductor layer. The P-type TFT includes a fifth semiconductor layer and a sixth semiconductor layer. A P-type doping concentration of the fifth semiconductor layer is smaller than that of the sixth semiconductor layer.