SHIFT REGISTER AND DRIVING METHOD THEREFOR, AND DISPLAY APPARATUS

    公开(公告)号:US20220335889A1

    公开(公告)日:2022-10-20

    申请号:US17760733

    申请日:2021-03-18

    Abstract: A shift register (SR) includes a voltage control circuit (110) and a bias compensation circuit (120). The voltage control circuit (110) is configured to control a voltage at a first node (Output) to be a first voltage or a second voltage. The bias compensation circuit (120) is configured to: when the voltage at the first node (Output) is the first voltage, transmit a first signal received by a first signal terminal (VDD-A) to a first signal output terminal (EM1), and transmit a second signal received by a second signal terminal (VDD-B) to a second signal output terminal (EM2); and in response to the voltage at the first node (Output) being the second voltage, transmit a signal received by a first voltage terminal (LVGL1) to the first signal output terminal (EM1) and the second signal output terminal (EM2).

    ARRAY SUBSTRATE, DRIVING METHOD THEREOF, AND DISPLAY APPARATUS

    公开(公告)号:US20220293037A1

    公开(公告)日:2022-09-15

    申请号:US17511335

    申请日:2021-10-26

    Abstract: Disclosed is an array substrate including multiple first selection circuits with each including at least two first selection transistors and at least two first anticreeping transistors. Each first selection transistor is connected with one first anticreeping transistor in series. When the first selection transistor is turned on by a first turn-on signal from a first control signal terminal, the first anticreeping transistor is turned on by a second turn-on signal from a second control signal terminal. When the first selection transistor is turned off by a first turn-off signal from the first control signal terminal, the first anticreeping transistor is turned off to make the first selection transistors and the data signal terminal disconnected, by a second turn-off signal from the second control signal terminal. A voltage of the first turn-off signal is greater than a voltage of the second turn-off signal.

    PIXEL DRIVING STRUCTURE AND DISPLAY PANEL

    公开(公告)号:US20220101783A1

    公开(公告)日:2022-03-31

    申请号:US17476798

    申请日:2021-09-16

    Abstract: The present disclosure provides a pixel driving structure and a display panel. The pixel driving structure includes a pulse width modulation driving circuit, a pulse amplitude modulation driving circuit, and a buffer circuit. The pulse width modulation driving circuit is configured to control a pulse width of a driving current supplied to the light emitting device to be driven according to a pulse width modulation data voltage; the pulse amplitude modulation driving circuit is configured to control an amplitude of the driving current supplied to the light emitting device to be driven according to a pulse amplitude modulation data voltage; and the buffer circuit is electrically coupled between the pulse width modulation driving circuit and the pulse amplitude modulation driving circuit and is configured to adjust a rate at which the pulse width modulation driving circuit applies a pulse width modulation voltage to the pulse amplitude modulation driving circuit.

    PIXEL DRIVING CIRCUIT, DRIVING METHOD THEREOF AND DISPLAY DEVICE

    公开(公告)号:US20210366389A1

    公开(公告)日:2021-11-25

    申请号:US16491547

    申请日:2019-03-28

    Abstract: A pixel driving circuit including: N pixel circuits each including a first node and a power supply terminal, N being an integer greater than 1; and N multiplexing circuits configured to selectively couple a data line to the first nodes of the N pixel circuits. A first one of the N multiplexing circuits includes a multiplexing control circuit, and a second one to an N-th one of the N multiplexing circuits include respective multiplexing control circuits and respective reset circuits. The reset circuit of a (j+1)-th one of the N multiplexing circuits is configured to reset the first node of a (j+1)-th one of the N pixel circuits with a power supply voltage in response to a j-th multiplexing control signal being active, j being an integer and 1≤j

    DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY ASSEMBLY

    公开(公告)号:US20210333654A1

    公开(公告)日:2021-10-28

    申请号:US16614343

    申请日:2019-05-15

    Abstract: A display substrate includes: a plurality of sub-pixel regions at a first base substrate, each of the plurality of sub-pixel regions including a light-blocking region and aperture regions located at opposing sides of the light-blocking region; and a first transparent electrode and a second transparent electrode within each of the plurality of sub-pixel regions, configured to drive a liquid crystal layer; wherein the first transparent electrode includes a first electrode unit located inside the light-blocking region and including a plurality of first sub-electrodes, wherein each of the plurality of first sub-electrodes are separated from two adjacent first sub-electrodes by a separation distance; and wherein the separation distance between two adjacent first sub-electrodes nearest to a center line of the light-blocking region is smaller than the separation distance between two adjacent first sub-electrodes nearest to an edge of the light-blocking region

    DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

    公开(公告)号:US20210057493A1

    公开(公告)日:2021-02-25

    申请号:US16916205

    申请日:2020-06-30

    Abstract: The present application relates to the field of display technology, and in particular, to a display panel, method for manufacturing a display panel and display device. The display panel includes: a base substrate; a pixel layer, provided on the base substrate and comprising a plurality of pixel islands; and a microlens layer, provided on a surface of the pixel layer facing away from the base substrate. Each of pixel islands includes a plurality of sub-pixels that emit light of a same color and are seamlessly coupled to each other, and the light emitted by the plurality of sub-pixels in each of the pixel islands is refracted by the microlens layer to be dispersed to different pixel areas

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