公开(公告)号：US07271867B2

公开(公告)日：2007-09-18

申请号：US10273073

申请日：2002-10-17

申请人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

发明人： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

IPC分类号： G02F1/1333 ,  G02F1/136

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/66765

摘要： A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes; and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, forming an under-layer on the first wiring line assembly, forming an organic insulating layer such that the organic insulating layer covers the under-layer, patterning the organic insulating layer to thereby form contact holes exposing the under-layer, etching the under-layer exposed through the contact holes such that the underlying first wiring line assembly is exposed to the outside, curing the organic insulating layer, and forming a second wiring line assembly on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the contact holes.

摘要翻译： 公开了一种器件及其相应的制造方法，其中器件为半导体和显示器件提供接触，该器件包括衬底，形成在衬底上的第一布线组件，形成在第一布线组件上的底层 形成在下层上的有机绝缘层，使得有机绝缘层覆盖下层，在有机绝缘层上形成用于接触孔的图案，以暴露下层中形成的下层的蚀刻接触孔， 与图案对应，使得下面的第一布线组件暴露于外部，形成在下层上的固化的有机绝缘层和形成在有机绝缘层上的第二布线组件，使得第二布线组件是 通过蚀刻的接触孔连接到第一布线组件; 以及相应的制造方法，包括在基板上形成第一布线线组件，在第一布线线路组件上形成底层，形成有机绝缘层，以使有机绝缘层覆盖下层，图案化有机绝缘层 从而形成暴露下层的接触孔，蚀刻通过接触孔暴露的下层，使得下面的第一布线线组件暴露于外部，固化有机绝缘层，并形成第二布线组件 所述有机绝缘层使得所述第二布线组合体通过所述接触孔连接到所述第一布线线组件。

公开(公告)号：US07119368B2

公开(公告)日：2006-10-10

申请号：US10926719

申请日：2004-08-26

申请人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

发明人： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC分类号： H01L31/0376

CPC分类号： G02F1/1368 ,  G02F1/1339

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US07023016B2

公开(公告)日：2006-04-04

申请号：US10884083

申请日：2004-07-01

申请人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

发明人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US20050110014A1

公开(公告)日：2005-05-26

申请号：US10922343

申请日：2004-08-19

申请人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

发明人： Min-Wook Park ,  Bum-Ki Baek ,  Jeong-Young Lee ,  Kwon-Young Choi ,  Sang-Ki Kwak ,  Sang-Jin Jeon

IPC分类号： G02F1/1339 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L23/52 ,  H01L29/417 ,  H01L29/786 ,  H01L31/036

CPC分类号： H01L29/41733 ,  H01L27/124

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

公开(公告)号：US08866142B2

公开(公告)日：2014-10-21

申请号：US13177259

申请日：2011-07-06

申请人： Sang-Jin Jeon ,  Gwang-Bum Ko

发明人： Sang-Jin Jeon ,  Gwang-Bum Ko

IPC分类号： H01L33/08 ,  H01L27/12

CPC分类号： H01L27/1225 ,  H01L27/124

摘要： The present invention relates to a display device and a manufacturing method thereof. A display device according to an exemplary embodiment of the present invention includes a substrate including a first surface and a second surface, a first line disposed on the first surface and made of a transparent metal oxide semiconductor, and a first semiconductor disposed on the first surface and made of the transparent metal oxide semiconductor.

摘要翻译： 显示装置及其制造方法技术领域本发明涉及显示装置及其制造方法。 根据本发明的示例性实施例的显示装置包括：基板，包括第一表面和第二表面;第一线，设置在第一表面上，由透明金属氧化物半导体制成，第一半导体设置在第一表面 并由透明金属氧化物半导体制成。

公开(公告)号：US20140011974A1

公开(公告)日：2014-01-09

申请号：US13980860

申请日：2012-01-19

申请人： Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An ,  Sang-Jin Jeon ,  Cheon-II Park ,  Choong-Hoon Lee

发明人： Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An ,  Sang-Jin Jeon ,  Cheon-II Park ,  Choong-Hoon Lee

IPC分类号： C08F210/16

CPC分类号： C08F295/00 ,  C08F4/64013 ,  C08F4/65904 ,  C08F4/6592 ,  C08F210/16 ,  C08F297/08 ,  C08L23/08 ,  C08L23/0815 ,  C08L23/14 ,  C08L23/142 ,  C08F4/64044 ,  C08F210/00

摘要： The present description relates to an olefin block copolymer having excellences in elasticity and heat resistance and its preparation method. The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. The olefin block copolymer has a density of 0.85 to 0.92 g/cm3, and density X (g/cm3) and TMA (Thermal Mechanical Analysis) value Y (° C.) satisfy a defined relationship.

摘要翻译： 本发明涉及具有优异的弹性和耐热性的烯烃嵌段共聚物及其制备方法。 烯烃嵌段共聚物包括多个嵌段或链段，每个嵌段或链段包括不同重量分数的乙烯或丙烯重复单元和α-烯烃重复单元。 烯烃嵌段共聚物的密度为0.85〜0.92g / cm 3，密度X（g / cm 3）和TMA（热机械分析）值Y（℃）满足规定的关系。

公开(公告)号：US20130296517A1

公开(公告)日：2013-11-07

申请号：US13980870

申请日：2012-01-20

申请人： Kyung-Seop Noh ,  Won-Hee Kim ,  Nan-Young Lee ,  Sang-Jin Jeon ,  Sang-Eun An

发明人： Kyung-Seop Noh ,  Won-Hee Kim ,  Nan-Young Lee ,  Sang-Jin Jeon ,  Sang-Eun An

IPC分类号： C08F297/08

CPC分类号： C08F297/083 ,  C08F4/65908 ,  C08F4/6592 ,  C08F210/16 ,  C08F301/00 ,  C08F2410/01 ,  C08F2500/10 ,  C08F4/65904 ,  C08F4/64044 ,  C08F210/14 ,  C08F2500/12 ,  C08F2500/08 ,  C08F2500/03

摘要： The present description relates to an olefin block copolymer having excellences in elasticity, heat resistance, and processability. The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. In the olefin block copolymer, a first derivative of the number Y of short-chain branches (SCBs) per 1,000 carbon atoms of each polymer chain contained in the block copolymer with respect to the molecular weight X of the polymer chains is a negative or positive number of −1.5×10−4 or greater; and the first derivative is from −1.0×10−4 to 1.0×10−4 in the region corresponding to the median of the molecular weight X or above.

摘要翻译： 本发明涉及具有优异的弹性，耐热性和加工性的烯烃嵌段共聚物。 烯烃嵌段共聚物包括多个嵌段或链段，每个嵌段或链段包括不同重量分数的乙烯或丙烯重复单元和α-烯烃重复单元。 在烯烃嵌段共聚物中，相对于聚合物链的分子量X，包含在嵌段共聚物中的每个聚合物链的每1000个碳原子的短链分支数（SCB）的第一个Y的一级导数是负的或正的 数量为-1.5×10-4以上; 在对应于分子量X或更高的中位数的区域中，第一衍生物为-1.0×10-4至1.0×10-4。

公开(公告)号：US08558776B2

公开(公告)日：2013-10-15

申请号：US11999329

申请日：2007-12-04

申请人： Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-Jin Jeon

发明人： Min-Cheol Lee ,  Hee-Bum Park ,  Yong-Soon Lee ,  Seung-Soo Baek ,  Sang-Jin Jeon

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3677 ,  G09G2320/0223

摘要： In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

摘要翻译： 在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。 阵列基板包括显示器和外围区域。 栅极和源极线形成在显示区域中。 在周边区域中形成栅极驱动部分和第一和第二时钟线。 栅极驱动部分将栅极信号输出到栅极线。 第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。 相对的衬底与阵列衬底组合并且包括公共电极层。 公共电极层具有图案化以暴露第一和第二时钟线的开口部分。 第一和第二时钟线的暴露部分具有基本上相同的面积。 因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

公开(公告)号：US07960732B2

公开(公告)日：2011-06-14

申请号：US12082495

申请日：2008-04-11

申请人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

发明人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20080191212A1

公开(公告)日：2008-08-14

申请号：US12082495

申请日：2008-04-11

申请人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

发明人： Jeong-Young Lee ,  Se-Hwan Yu ,  Sang-Jin Jeon ,  Min-Wook Park

IPC分类号： H01L29/04

CPC分类号： H01L27/12 ,  G02F1/13458 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1288

摘要： A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

摘要翻译： 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在所述下导电膜的第一部分上形成像素电极; 去除下导电膜的第二部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。