Integrated microchannel synthesis and separation
    21.
    发明授权
    Integrated microchannel synthesis and separation 有权
    集成微通道的合成和分离

    公开(公告)号:US08497308B2

    公开(公告)日:2013-07-30

    申请号:US12439872

    申请日:2007-09-05

    Abstract: A process for carrying out at least two unit operations in series, the process comprising the step of: (a) directing a feed stream into an integrated assembly which comprises a first microchannel unit operation upon at least one chemical of the feed stream to generate a distributed output stream that exits the first microchannel unit operation in a first set of discrete microchannels isolating flow through the discrete microchannels; and (b) directing the distributed output stream of the first microchannel unit operation into a second microchannel unit operation as a distributed input stream, to continue isolating flow between the first set of discrete microchannels, and conducting at least one operation upon at least one chemical of the input stream to generate a product stream that exits the second microchannel unit operation, where the first microchannel unit operation and the second unit operation share a housing.

    Abstract translation: 一种用于串联进行至少两个单元操作的方法,该方法包括以下步骤:(a)将进料流引导到集成组件中,其包括在进料流的至少一种化学品上的第一微通道单元操作以产生 在第一组离散微通道中离开第一微通道单元操作的分布式输出流,其隔离通过离散微通道的流动; 和(b)将第一微通道单元操作的分布式输出流引导到作为分布式输入流的第二微通道单元操作中,以继续隔离第一组离散微通道之间的流动,并且至少一种化学物质进行至少一种操作 以产生离开第二微通道单元操作的产品流,其中第一微通道单元操作和第二单元操作共享外壳。

    Method to form uniform silicide by selective implantation
    22.
    发明授权
    Method to form uniform silicide by selective implantation 有权
    通过选择性植入形成均匀硅化物的方法

    公开(公告)号:US08492275B2

    公开(公告)日:2013-07-23

    申请号:US13186519

    申请日:2011-07-20

    Abstract: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

    Abstract translation: 方法通过在衬底内和/或衬底上形成多个器件的至少一部分形成集成电路结构,并且在邻近器件的衬底上的层间电介质层中图案化沟槽。 图案形成相对较窄的沟槽和较宽的沟槽。 然后,所述方法对沟槽进行补偿材料的成角度注入。 成角度的植入物的角度相对于在较窄沟槽的底部注入衬底的区域中的补偿材料的量,在较宽沟槽底部的衬底区域中植入更大浓度的补偿材料。 然后,该方法将金属材料沉积在沟槽内,并加热金属材料以从金属材料形成硅化物。

    Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device
    25.
    发明授权
    Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device 失效
    具有减小的结漏电的半导体器件和形成这种半导体器件的相关方法

    公开(公告)号:US08349716B2

    公开(公告)日:2013-01-08

    申请号:US12911186

    申请日:2010-10-25

    Abstract: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

    Abstract translation: 公开了一种具有p-n结的半导体器件,其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。 具体地说,形成具有p-n结的半导体层。 在半导体层上形成金属硅化物层,并且将掺杂剂注入到金属硅化物层中。 执行退火处理,使掺杂剂朝向金属硅化物半导体层界面迁移,使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。 结果,硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度,这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

    GLUCAGON ANTAGONISTS
    29.
    发明申请

    公开(公告)号:US20120122783A1

    公开(公告)日:2012-05-17

    申请号:US12739342

    申请日:2008-10-23

    CPC classification number: C07K14/605 A61K38/00

    Abstract: Glucagon antagonists are provided which comprise amino acid substitutions and/or chemical modifications to glucagon sequence. In one embodiment, the glucagon antagonists comprise a native glucagon peptide that has been modified by the deletion of the first two to five amino acid residues from the N-terminus and (i) an amino acid substitution at position 9 (according to the numbering of native glucagon) or (ii) substitution of the Phe at position 6 (according to the numbering of native glucagon) with phenyl lactic acid (PLA). In another embodiment, the glucagon antagonists comprise the structure A-B-C as described herein, wherein A is PLA, an oxy derivative thereof, or a peptide of 2-6 amino acids in which two consecutive amino acids of the peptide are linked via an ester or ether bond.

    Abstract translation: 提供了包含对胰高血糖素序列的氨基酸取代和/或化学修饰的胰高血糖素拮抗剂。 在一个实施方案中,胰高血糖素拮抗剂包含通过从N-末端缺失前两个至五个氨基酸残基而修饰的天然胰高血糖素肽,以及(i)在第9位的氨基酸取代(根据 天然胰高血糖素)或(ii)用苯基乳酸(PLA)取代第6位的Phe(根据天然胰高血糖素的编号)。 在另一个实施方案中,胰高血糖素拮抗剂包含如本文所述的结构ABC,其中A是PLA,其氧衍生物或2-6个氨基酸的肽,其中肽的两个连续氨基酸经由酯或醚连接 键。

    SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE
    30.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDUCED JUNCTION LEAKAGE AND AN ASSOCIATED METHOD OF FORMING SUCH A SEMICONDUCTOR DEVICE 失效
    具有降低接合泄漏的半导体器件和形成这种半导体器件的相关方法

    公开(公告)号:US20120098042A1

    公开(公告)日:2012-04-26

    申请号:US12911186

    申请日:2010-10-25

    Abstract: Disclosed is a semiconductor device having a p-n junction with reduced junction leakage in the presence of metal silicide defects that extend to the junction and a method of forming the device. Specifically, a semiconductor layer having a p-n junction is formed. A metal silicide layer is formed on the semiconductor layer and a dopant is implanted into the metal silicide layer. An anneal process is performed causing the dopant to migrate toward the metal silicide-semiconductor layer interface such that the peak concentration of the dopant will be within a portion of the metal silicide layer bordering the metal silicide-semiconductor layer interface and encompassing the defects. As a result, the silicide to silicon contact is effectively engineered to increase the Schottky barrier height at the defect, which in turn drastically reduces any leakage that would otherwise occur, when the p-n junction is in reverse polarity.

    Abstract translation: 公开了一种具有p-n结的半导体器件,其在存在延伸到结的金属硅化物缺陷的情况下具有减少的结漏电以及形成器件的方法。 具体地说,形成具有p-n结的半导体层。 在半导体层上形成金属硅化物层,并且将掺杂剂注入到金属硅化物层中。 执行退火处理,使掺杂剂朝向金属硅化物半导体层界面迁移,使得掺杂剂的峰值浓度将在金属硅化物层的与金属硅化物半导体层界面接壤并包围缺陷的部分内。 结果,硅化物与硅接触被有效地设计以增加缺陷处的肖特基势垒高度,这反过来大大降低了当p-n结处于相反极性时将会发生的任何泄漏。

Patent Agency Ranking