公开(公告)号：US20170278473A1

公开(公告)日：2017-09-28

申请号：US15512284

申请日：2016-02-19

Applicant: Boe Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Haoliang Zheng

IPC: G09G3/36 ,  G11C19/28 ,  G11C19/18 ,  G11C8/04

CPC classification number: G09G3/3674 ,  G09G3/36 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2330/06 ,  G11C8/04 ,  G11C19/184 ,  G11C19/28 ,  G11C19/287

Abstract: A shift register, a driving method, a gate driving circuit and a display device are disclosed. The input module controls the potential of the first node. The first reset module controls the potential of the first node. The second reset module controls the potential of the driving signal output terminal. The first output module controls the potential of the driving signal output terminal under the control of the first node. The second output module controls the potential of the driving signal output terminal under the control of the second node. The pull-down driving module controls the potentials of the first node and the second node. Since the node control signal at the node control signal terminal can eliminate the noise on the first node resulting from the change in the first clock signal, the output stability of the shift register can be improved.

公开(公告)号：US20170213497A1

公开(公告)日：2017-07-27

申请号：US15326370

申请日：2015-12-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seung Woo Han ,  Mingfu Han ,  Haoliang Zheng ,  Yanfeng Wang

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/20 ,  G09G2300/0408 ,  G09G2300/08 ,  G09G2310/0248 ,  G09G2310/0267 ,  G09G2310/08 ,  G09G2330/021

Abstract: The present disclosure discloses a GOA unit driving circuit and a driving method thereof, a display panel and a display device. The disclosure relates to field of display technology, and solves the technical issue of increased power consumption of the display device due to the power consumption of the parasitic capacitance existing in the transistors in the GOA unit. The GOA unit driving circuit comprises a plurality of sets of GOA units, each of which includes at least one GOA unit; a plurality of clock selecting units, which are in one-to-one correspondence with the plurality of sets of GOA units, and each clock selecting unit is connected to a corresponding set of GOA units and connected to one of a plurality of clock signal terminals and at least one of a plurality of clock selection signal terminals, respectively. An intersection of any two sets of GOA units in the plurality of sets of GOA unit is an empty set, and each clock selecting unit transmits a signal of the clock signal terminal to which the clock selecting unit is connected to the corresponding set of GOA units, under control of a signal of the at least one clock selection signal terminal to which the clock selecting unit is connected. The GOA unit driving circuit provided by the present disclosure may be applied to a display device.

公开(公告)号：US20160359055A1

公开(公告)日：2016-12-08

申请号：US14785606

申请日：2015-04-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L27/12 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/7869

Abstract: A metal oxide thin film transistor and a preparation method thereof, as well as an array substrate, wherein the metal oxide thin film transistor comprises a base substrate, an active layer and a source-drain metal layer formed on the base substrate that contact each other and are located in different layers, the source-drain metal layer comprising separated source electrode and drain electrode; the active layer having a hollow structure in a channel area located between the source electrode and the drain electrode.

Abstract translation: 一种金属氧化物薄膜晶体管及其制备方法以及阵列基板，其中，所述金属氧化物薄膜晶体管包括形成在所述基底基板上的基极基板，有源层和源极 - 漏极金属层，所述基极基板彼此接触 并且位于不同的层中，源极 - 漏极金属层包括分离的源电极和漏电极; 所述有源层在位于所述源电极和所述漏电极之间的沟道区域中具有中空结构。

公开(公告)号：US09460672B2

公开(公告)日：2016-10-04

申请号：US14103234

申请日：2013-12-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Lilei Zhang

IPC: G09G3/36 ,  G09G3/00

CPC classification number: G09G3/3648 ,  G09G3/003 ,  G09G3/3607 ,  G09G3/3614 ,  G09G2300/0452

Abstract: The present invention provides a method for driving a liquid crystal display panel and a liquid crystal display so that the power consumption for driving a 3D liquid crystal display panel can be reduced. The method includes steps of: determining that it is needed to input data to the black matrix sub-pixels when displaying a 3D image; and inputting a control signal to a 3D black screen data control module, the 3D black screen data control module, based on the received control signal, makes two data lines which are connected therewith and are of opposite polarities be electrically conducted.

Abstract translation: 本发明提供一种用于驱动液晶显示面板和液晶显示器的方法，从而可以降低用于驱动3D液晶显示面板的功耗。 该方法包括以下步骤：确定在显示3D图像时需要向黑矩阵子像素输入数据; 并且将控制信号输入到3D黑屏数据控制模块，3D黑屏数据控制模块基于接收到的控制信号，使与之连接并具有相反极性的两条数据线被电导通。

公开(公告)号：US12183256B2

公开(公告)日：2024-12-31

申请号：US18466619

申请日：2023-09-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Jie Zhang ,  Jiangnan Lu ,  Mei Li ,  Libin Liu

IPC: G09G3/20 ,  G09G3/3266

Abstract: A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit controls to connect or disconnect the input terminal and the first input node under the control of a clock signal provided by the clock signal terminal; the charge pump circuit controls to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal.

公开(公告)号：US20240161669A1

公开(公告)日：2024-05-16

申请号：US17781988

申请日：2021-03-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Libin Liu ,  Long Han ,  Yu Feng

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/20 ,  G11C19/28 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0209 ,  G09G2320/0233 ,  G09G2330/021

Abstract: A display substrate and a display device are provided. The display substrate includes a shift register unit, a first clock signal line and a first power line, the shift register unit includes a charge pump circuit, and the charge pump circuit includes a first capacitor, a first transistor and a second capacitor. The charge pump circuit is electrically connected with a first input node and a first node, respectively. A first electrode plate of the first capacitor is connected with the first clock signal line, a second electrode plate of the first capacitor is connected with the first input node, a first electrode plate of the second capacitor is connected with the first power line, a second electrode plate of the second capacitor is connected with the first node, a gate electrode of the first transistor is connected with a first electrode or a second electrode of the first transistor.

公开(公告)号：US20230343285A1

公开(公告)日：2023-10-26

申请号：US17764395

申请日：2021-03-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Xinshe Yin ,  Libin Liu ,  Jianchao Zhu ,  Hao Zhang ,  Ke Feng

IPC: G09G3/3233 ,  G11C19/28

CPC classification number: G09G3/3233 ,  G11C19/28 ,  G09G2310/0286 ,  G09G2300/0842 ,  G09G2310/08

Abstract: A shift register unit, a driving method thereof, a gate driving circuit and a display panel are provided. The shift register unit includes an input circuit, a reset circuit, a first output circuit and a second output circuit; the input circuit is configured to control a level of a first node in response to a first input signal; the reset circuit is configured to reset the first node in response to a reset signal; the first output circuit is configured to output a shift signal under control of the level of the first node; and the second output circuit is configured to, in a first phase, under control of the level of the first node, output a plurality of sub-pulses at the first output terminal as a first output signal in a case where the shift output terminal outputs a first level of the shift signal.

公开(公告)号：US11574597B2

公开(公告)日：2023-02-07

申请号：US17426949

申请日：2020-10-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng ,  Yu Feng ,  Guangliang Shang ,  Libin Liu ,  Shiming Shi

IPC: G09G3/3266 ,  G09G3/20

Abstract: A gate driving unit, a gate driving circuit, a gate driving method, and a display device are provided. The gate driving unit includes a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit; the first output circuit is respectively electrically connected to the first node, the second node and the first gate driving signal output end and is configured to control the first gate driving signal output end to output a first gate driving signal under the control of the potential of the first node and the potential of the second node; the first output sub-circuit is respectively electrically connected to the first node, the second gate driving signal output end and the first clock signal end, and is configured to control the second gate driving signal output end to be connected to the first clock signal end.

公开(公告)号：US11282424B2

公开(公告)日：2022-03-22

申请号：US16301843

申请日：2018-04-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seungwoo Han

IPC: G09G3/20 ,  G01B7/16 ,  G09G3/00 ,  G06F3/03

Abstract: The present disclosure is related to a flexible display panel. The flexible display panel may include a display substrate, a plurality of pixel units arranged in an array on the display substrate, and at least a strain sensor on the display substrate. The strain sensor may be arranged corresponding to a region comprising at least one of the plurality of pixel units. The strain sensor may be configured to detect deformation in the region comprising at least one of the plurality of pixel units and to generate a detection signal.

公开(公告)号：US11227521B2

公开(公告)日：2022-01-18

申请号：US16652180

申请日：2019-10-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng ,  Libin Liu ,  Li Wang ,  Tian Dong ,  Guangliang Shang ,  Xinshe Yin

IPC: G09G3/00

Abstract: The present disclosure relates to a gate driving circuit applied to a foldable display panel comprising B display areas arranged in order. The gate driving circuit may include B gate driving subcircuits and a control circuit. Each of the gate driving subcircuits may correspond to one of the display areas and each of the gate driving subcircuits may comprise a plurality of stage gate driving units. The control circuit may be configured to, when the foldable display panel is in a full screen display state, control a type of an input signal in a last stage gate driving unit of a bth gate driving subcircuit to be the same as a type of an input signal in a first stage gate driving unit of a (b+1)th gate driving subcircuit, where B is an integer greater than 1 and b is a positive integer less than B.