公开(公告)号：US20210341780A1

公开(公告)日：2021-11-04

申请号：US16335862

申请日：2018-09-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xue Dong ,  Liwei Liu ,  Xinxing Wang ,  Yun Sik Im ,  Hyun Sic Choi ,  Jaegeon You ,  Yinglong Huang ,  Heecheol Kim

IPC: G02F1/1339 ,  H01L27/12 ,  G02F1/1335 ,  G02F1/1368 ,  G02F1/1362

Abstract: A display panel and a display device are provided. In the display panel, a plurality of main spacers and a plurality of auxiliary spacers are disposed on a side of a first substrate close to a second substrate, the second substrate further includes a plurality of first lug bosses and a plurality of second lug bosses; an orthographic projection of the main spacers on the second substrate is at least partially overlapped with an orthographic projection of a corresponding first lug boss on the second substrate; an orthographic projection of the auxiliary spacers on the second substrate is away from an orthographic projection of a corresponding second lug boss on the second substrate by a preset distance; and the distance between each of the auxiliary spacers and the corresponding second lug boss is less than a height of the first lug bosses.

公开(公告)号：US10783816B2

公开(公告)日：2020-09-22

申请号：US16234647

申请日：2018-12-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Xing Dong ,  Heecheol Kim ,  Zhi Zhang ,  Xiuzhu Tang ,  Shuai Chen ,  Lijun Xiong ,  Jingpeng Zhao ,  Taoliang Tang ,  Min Ran

IPC: G09G3/20

Abstract: An amplitude control main circuit, a voltage supply modular circuit, a display device, and an amplitude control method are provided. The amplitude control main circuit includes a variable resistive circuit, an output control circuit and a gate-driving-power-voltage output terminal; the output control circuit is connected to an output control terminal, a voltage input terminal, the gate-driving-power-voltage output terminal, and the variable resistive circuit, and controls, under control of the output control terminal, the gate-driving-power-voltage output terminal to be connected to the voltage input terminal directly or via the variable resistive circuit; a control terminal, a first terminal, and a second terminal of the variable resistive circuit are connected to a resistance control terminal, the output control circuit, and the gate-driving-power-voltage output terminal, respectively, and a resistance value of the variable resistive circuit is changed under control of the resistance control terminal.

公开(公告)号：US20190051679A1

公开(公告)日：2019-02-14

申请号：US16160223

申请日：2018-10-15

Applicant: BOE Technology Group Co., Ltd.

Inventor： Seongyeol Yoo ,  Seungjin Choi ,  Heecheol Kim ,  Youngsuk Song

IPC: H01L27/12

Abstract: Disclosed is an array substrate and a display device. The array substrate includes: a plurality of gate lines and a plurality of data lines formed on a base substrate, and a plurality of pixel units defined by the plurality of gate lines and the plurality of data lines intersecting each other, wherein each pixel unit includes a thin film transistor and a pixel electrode connected with the thin film transistor, the pixel electrode, the data line, as well as an active layer, a source and a drain of the thin film transistor are disposed in a same layer and are formed through a single patterning process,

公开(公告)号：US10191330B2

公开(公告)日：2019-01-29

申请号：US14895091

申请日：2015-05-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Heecheol Kim ,  Hyun Sic Choi

IPC: G02F1/1337 ,  G02F1/1341 ,  G02F1/1343 ,  G02F1/1333

Abstract: A liquid crystal display panel, a fabrication method thereof and a display device are provided. The liquid crystal display panel comprises: an opposed substrate (10) and an array substrate (20) arranged opposite to each other, and a liquid crystal layer (30) filled between the opposed substrate (10) and the array substrate (20). Alignment films (40) having opposite friction directions are provided on opposing surfaces of the opposed substrate (10) and the array substrate (20), respectively. The liquid crystal display panel has a plurality of pixel units which are arranged in array, and each of the pixel units comprises two pixel regions (A, B) along the friction direction of the alignment film. In each of the pixel units, a surface of the opposed substrate (10) facing the liquid crystal layer (30) or a surface of the array substrate (20) facing the liquid crystal layer (30) within at least one of the two pixel regions is inclined, so that a mean value of included angles between long axes of liquid crystal molecules in the liquid crystal layer within one of the two pixel regions and a horizontal plane where the opposed substrate (10) and the array substrate (20) are located and a mean value of included angles between long axes of liquid crystal molecules in the liquid crystal layer within the other of the two pixel regions and the horizontal plane where the opposed substrate (10) and the array substrate (20) are located has a same absolute value and a sum of zero.

公开(公告)号：US09921361B2

公开(公告)日：2018-03-20

申请号：US14499634

申请日：2014-09-29

Applicant: Boe Technology Group Co., Ltd.

Inventor： Shang Wang ,  Heecheol Kim ,  Wei Qin

IPC: G09G3/34 ,  F21V8/00 ,  G02F1/1333 ,  G09G3/3258 ,  G09G3/3225 ,  G02F1/1335

CPC classification number: G02B6/0045 ,  G02B6/0055 ,  G02B6/0073 ,  G02F1/13336 ,  G02F1/133524 ,  G02F2001/133562 ,  G09G3/3225 ,  G09G3/3258 ,  G09G2300/0809 ,  G09G2310/0232 ,  G09G2320/0233 ,  G09G2320/029 ,  G09G2320/0626 ,  G09G2360/147

Abstract: The disclosure relates to the field of liquid crystal display, specifically to a display screen frame eliminating apparatus and a display device. The display screen frame eliminating apparatus comprises a light source, a light tube and a drive module. The light tube comprises an upper surface and a lower surface, and the light source is located within the light tube or under the lower surface of the light tube. The light tube enables the light emitted by the light source to dispersedly exit from the upper surface. The drive module drives the light source to emit light based on the luminous condition of the edge pixels of the display area in the display screen. In this way, the light source emits light rays similar as the edge pixels of the display area in the display screen, and the light rays dispersedly exit from the upper surface of the light tube by means of the layered light tube structure. Therefore, to the human eyes, the display influence of the frame can be eliminated in all directions, and the display effect of the display device can be improved.

公开(公告)号：US09824662B2

公开(公告)日：2017-11-21

申请号：US13948338

申请日：2013-07-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chao Xu ,  Chunfang Zhang ,  Yan Wei ,  Heecheol Kim

IPC: G09G3/36 ,  H01L23/48 ,  G02F1/1362

CPC classification number: G09G3/3696 ,  G02F1/136286 ,  G09G2320/0209 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a Thin Film Transistor Array Substrate and a Liquid Crystal Display apparatus thereof, and relates to the technical field of liquid crystal displaying. The Thin Film Transistor Array Substrate of the present disclosure includes a plurality of gate lines and a plurality of data lines, wherein regions surrounded by the gate lines and the data lines are pixel regions, and wherein a high level common voltage line being used when signal on the data line is at a low level and a low level common voltage lines being used when signal on the data line is at a high level are also arranged in parallel to the gate lines in each of the pixel regions. With the Thin Film Transistor Array Substrate of the present disclosure, the Greenish phenomenon in the existing liquid crystal display apparatus may be effectively solved.

公开(公告)号：US09804453B2

公开(公告)日：2017-10-31

申请号：US14422749

申请日：2014-04-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hyunsic Choi ,  Heecheol Kim

IPC: G02F1/1343 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1368 ,  G02F1/1339 ,  G02F1/1362

CPC classification number: G02F1/134363 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1339 ,  G02F1/134309 ,  G02F1/1368 ,  G02F2001/13398 ,  G02F2001/134381 ,  G02F2001/136222 ,  G02F2201/121 ,  G02F2202/16

Abstract: The embodiment of the present invention discloses a display device, which relates to the field of display, may realize low-frequency (low-standing-wave) driving and may prevent the aperture ratio from being reduced as a result of ensuring the charge rate during high-frequency driving. The display device provided by the present invention comprises a first substrate and a second substrate which are assembled with each other to form a cell, wherein the first substrate comprises a first electrode layer, the second substrate comprises a second electrode layer, the first substrate further comprises a third electrode layer arranged on one side, far from the second substrate, of the first electrode layer, and an insulation layer is arranged between the third electrode layer; and the first electrode layer, and the third electrode layer is electrically connected with the second electrode layer. The display device is suitable for being driven at low frequency.

公开(公告)号：US09786238B2

公开(公告)日：2017-10-10

申请号：US14354952

申请日：2013-12-27

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yoonsung Um ,  Heecheol Kim ,  Yunsik Im

IPC: G09G3/36 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1333 ,  G02F1/1362

CPC classification number: G09G3/3655 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13452 ,  G02F1/136286 ,  G02F2001/134345 ,  G09G3/3614 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/08 ,  G09G2310/0213 ,  G09G2310/0221 ,  G09G2320/0204 ,  G09G2320/0209

Abstract: According to the array substrate provided by this disclosure, in a row of sub-pixels, sub-pixels in the odd columns and even columns are separately coupled to different gate lines, i.e., making the sub-pixels coupled to the same gate line are not adjacent to each other. In this way, during row scanning drive, an up-down twist charging may be implemented, and the sub-pixels cause no interference to each other.

公开(公告)号：US09659978B2

公开(公告)日：2017-05-23

申请号：US14935351

申请日：2015-11-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chao Xu ,  Heecheol Kim

IPC: H01L29/12 ,  H01L29/04 ,  H01L21/00 ,  H01L27/12

CPC classification number: H01L27/1259 ,  H01L27/1255

Abstract: An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode.

公开(公告)号：US09653608B2

公开(公告)日：2017-05-16

申请号：US14409179

申请日：2014-05-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Seungjin Choi ,  Heecheol Kim ,  Youngsuk Song ,  Seongyeol Yoo

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: An array substrate and a manufacturing method thereof, a display device and a thin film transistor are provided. The method includes forming a pattern that includes an active layer, a pixel electrode and a data line on a base substrate; forming a pattern that includes a gate insulating layer and at least two gate via-holes therein, the at least two gate via-holes are located in regions in the gate insulating layer that correspond to outer surroundings of the active layer and do not overlap with areas where the pixel electrode and the data line are located; forming a pattern that includes a gate line and at least two gate electrodes, the at least two gate electrodes are connected to the gate line, and are provided in the at least two gate via-holes, respectively. With this method, the fabricating process and the fabricating cost are saved.