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21.发明申请Strained Semiconductor Structures and Method of Fabricating Strained Semiconductor Structures 有权应变半导体结构和制造应变半导体结构的方法公开(公告)号：US20110198695A1
公开(公告)日：2011-08-18
申请号：US12707975
申请日：2010-02-18
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/0649 , H01L29/4238 , H01L29/7842 , H01L29/7848 , H01L29/7849 , H01L29/785
摘要： A strained semiconductor structure and method of making the structure. The method includes: forming a pad layer on a top surface of a silicon layer of a substrate, the substrate comprising the silicon layer separated from a supporting substrate by a buried oxide layer; forming openings in the pad layer and etching trenches through the silicon layer to the buried oxide layer in the openings to form silicon regions from the silicon layer; forming spacers on the entirety of sidewalls of the silicon regions exposed in the trenches; forming oxide regions in corners of the silicon regions proximate to both the sidewalls and the buried oxide layer to form strained silicon regions, the oxide regions not extending to the pad layer; and removing at least a portion of the spacers and filling remaining spaces in the trenches with silicon to form filled regions abutting the strained silicon region.
摘要翻译： 一种应变半导体结构及其制造方法。 该方法包括：在衬底的硅层的顶表面上形成焊盘层，所述衬底包括通过掩埋氧化物层从支撑衬底分离的硅层; 在所述焊盘层中形成开口并且蚀刻通过所述硅层的沟槽到所述开口中的所述掩埋氧化物层，以从所述硅层形成硅区域; 在暴露在沟槽中的硅区域的整个侧壁上形成间隔物; 在接近两个侧壁和掩埋氧化物层的硅区域的角落中形成氧化物区域，以形成应变硅区域，氧化物区域不延伸到焊盘层; 并且移除至少一部分间隔物并用硅填充沟槽中的剩余空间以形成邻近应变硅区的填充区。
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22.发明授权Method for fabricating a field effect transistor having a dual thickness gate electrode 有权制造具有双厚度栅电极的场效应晶体管的方法公开(公告)号：US07851315B2
公开(公告)日：2010-12-14
申请号：US12037113
申请日：2008-02-26
IPC分类号： H01L21/336
CPC分类号： H01L29/42384 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.
摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 场效应晶体管包括：硅体，硅体的周边抵靠电介质隔离; 源体和漏极，其形成在主体中并形成在主体中的通道的相对侧上; 以及位于主体和导电栅电极之间的栅极电介质层，栅极电介质层的与表面主体直接物理接触的底表面和栅电极与 所述栅极电介质层，所述栅电极具有第一厚度的第一区域和具有第二厚度的第二区域，所述第一区域沿着所述沟道区域上的所述栅极电介质层的顶表面延伸，所述第二厚度大于所述第一厚度 厚度。
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公开(公告)号：US07821109B2
公开(公告)日：2010-10-26
申请号：US12570045
申请日：2009-09-30
IPC分类号： H01L23/58
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76832 , H01L29/7843
摘要： A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.
摘要翻译： 制作结构的结构和方法。 该结构包括场效应晶体管，包括：形成在硅衬底中的第一和第二源极/漏极，第一和第二源极/漏极间隔开并由衬底中的沟道区分隔开; 位于所述沟道区上的所述衬底顶表面上的栅电介质; 以及在所述栅极电介质的顶表面上的导电栅极; 以及栅极上的第一介电材料的介电柱; 以及介于第一和第二源极/漏极之间的第二介电材料的电介质层，介电柱的侧壁与电介质层直接物理接触，该介电柱不具有内部应力或不同于内部应力的内部应力 电介质层。
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公开(公告)号：US20100013019A1
公开(公告)日：2010-01-21
申请号：US12570045
申请日：2009-09-30
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76832 , H01L29/7843
摘要： A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.
摘要翻译： 制作结构的结构和方法。 该结构包括场效应晶体管，包括：形成在硅衬底中的第一和第二源极/漏极，第一和第二源极/漏极间隔开并由衬底中的沟道区分隔开; 位于所述沟道区上的所述衬底顶表面上的栅电介质; 以及在所述栅极电介质的顶表面上的导电栅极; 以及栅极上的第一介电材料的介电柱; 以及介于第一和第二源极/漏极之间的第二介电材料的电介质层，介电柱的侧壁与电介质层直接物理接触，该介电柱不具有内部应力或不同于内部应力的内部应力 电介质层。
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公开(公告)号：US07635656B2
公开(公告)日：2009-12-22
申请号：US11427419
申请日：2006-06-29
IPC分类号： H01L21/00
CPC分类号： B23K26/0626 , B23K26/0608 , H01L21/26513 , H01L21/2686
摘要： A method for configuring J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≦I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. in each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources, Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1−S1|, |V2−S2|, . . . , |Vi−Si| is about minimized with respect to Pi (i=1, . . . , I).
摘要翻译： 一种用于配置J电磁辐射源（J> = 2）以串行照射衬底的方法。 每个源具有不同的发射辐射的波长和角分布的功能。 衬底包括基层，I堆叠（I> = 2; J i）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。 在I独立曝光步骤的每一个中，I堆叠同时暴露于来自J源的辐射，Vi和Si分别表示在曝光步骤i（i = 1，...）中通过堆叠i传输到衬底中的实际和目标能量通量。 。 ， 一世）。 计算t（i）和Pt（i），使得：与部署i = 1的任何其他源相比，通过部署源t（i），Vi最大。 。 。 ， 一世; 并且误差E是| V1-S1 |，| V2-S2 |的函数。 。 。 ，| Vi-Si | 相对于Pi（i = 1，...，I）被最小化。
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公开(公告)号：US20090263949A1
公开(公告)日：2009-10-22
申请号：US12104475
申请日：2008-04-17
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer, and (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region. Next, a patterned covering layer is used to cover the first and second surfaces but not the third and fourth surfaces. Then, the first and second source/drain portions are etched at the third and fourth surfaces, respectively.
摘要翻译： 一种结构形成方法。 首先，提供一种结构，其包括（a）翅片区域，其包括：（i）第一源极/漏极部分，其具有彼此平行的第一表面和第三表面，不共面，并且暴露于周围环境;（ii） 第二源极/漏极部分，具有彼此平行的第二表面和第四表面，不共面，并暴露于周围环境;以及（iii）设置在第一和第二源极/漏极部分之间的沟道区域，（b ）栅介质层，和（c）栅电极区，其中所述栅介质层（i）夹在其间，和（ii）使所述栅电极区和所述沟道区电绝缘。 接下来，使用图案化覆盖层来覆盖第一表面和第二表面而不是第三表面和第四表面。 然后，分别在第三和第四表面处蚀刻第一和第二源极/漏极部分。
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公开(公告)号：US20080282209A1
公开(公告)日：2008-11-13
申请号：US11744980
申请日：2007-05-07
IPC分类号： G06F17/50
CPC分类号： G06F21/73 , H01L23/544 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： A verification system disclosed herein uses the unique signatures of an IC to perform authentication of the IC after the IC is shipped to a customer. The verification system records the fingerprint and associated IC identifier with the fingerprint into a data structure. The data structure is supplied to the customer for use in the customer's own security systems. When an IC interfaces with the customer's system, the verification system requests the IC's identifier and selects a data structure corresponding to that IC identifier. The verification system then performs a test on the IC (e.g. remotely operates the IC at 1V), records the resulting data and compares the test results with the corresponding data in the data structure. If a predetermined condition is satisfied then the IC is verified to be authentic. If not, the verification system responds, for example, by flagging the customer's security system.
摘要翻译： 本文公开的验证系统使用IC的唯一签名来在IC被发送给客户之后执行IC的认证。 验证系统将指纹和相关联的IC标识符与指纹记录到数据结构中。 数据结构提供给客户，以供客户自己的安全系统使用。 当IC与客户系统接口时，验证系统请求IC的标识符并选择与该IC标识对应的数据结构。 然后，验证系统对IC进行测试（例如，以1V远程操作IC），记录所得到的数据，并将测试结果与数据结构中的对应数据进行比较。 如果满足预定条件，则IC被验证为可信。 如果没有，则验证系统例如通过标记客户的安全系统来做出响应。
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28.发明申请公开(公告)号：US20080272457A1
公开(公告)日：2008-11-06
申请号：US11744248
申请日：2007-05-04
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L21/84 , H01L21/823481 , H01L27/0207 , H01L27/0617 , H01L27/08 , H01L27/1203
摘要： A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.
摘要翻译： 一种结构及其形成方法。 该结构包括（a）包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面的衬底，（b）衬底上的N个半导体区域，以及（c）衬底上的P个半导体区域，N和P 正整数。 N个半导体区域包括掺杂剂。 P半导体区域不包含掺杂剂。 该结构还包括在衬底的顶部上的M个互连层，N个半导体区域和P个半导体区域，M是正整数。 M互连层包括电感器。 （i）N个半导体区域不重叠，（ii）P个半导体区域在参考方向上与电感器重叠。 垂直于基准方向并且与N个半导体区域的半导体区域交叉的平面与P半导体区域的半导体区域相交。
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公开(公告)号：US20080246097A1
公开(公告)日：2008-10-09
申请号：US12117014
申请日：2008-05-08
申请人： Brent Alan Anderson , Shahid Ahmad Butt , Allen H. Gabor , Patrick Edward Lindo , Edward Joseph Nowak , Jed Hickory Rankin
发明人： Brent Alan Anderson , Shahid Ahmad Butt , Allen H. Gabor , Patrick Edward Lindo , Edward Joseph Nowak , Jed Hickory Rankin
IPC分类号： H01L27/088
CPC分类号： H01L22/20
摘要： A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.
摘要翻译： 一种降低参数变化减小的集成电路（IC）芯片和IC芯片的参数变化的方法。 该方法包括：在具有第一芯片布置的第一晶片上，将每个IC芯片分成第二区域布置，测量分布在不同区域中的测试装置的测试装置参数; 并且在具有IC芯片的第一布置和第二区域布置的第二晶片上，基于测试值调整第二晶片的所有IC芯片的一个或多个区域内相同设计的场效应晶体管的功能器件参数 在第一晶片的IC芯片的区域中的测试装置上测量的器件参数通过在每个IC芯片内的区域到区域的相同设计的场效应晶体管的物理或冶金多晶硅栅极宽度的不均匀调整而不均匀地调整。
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公开(公告)号：US20080203448A1
公开(公告)日：2008-08-28
申请号：US11679880
申请日：2007-02-28
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/76801 , H01L21/76832 , H01L29/7843
摘要： A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer.
摘要翻译： 制作结构的结构和方法。 该结构包括场效应晶体管，包括：形成在硅衬底中的第一和第二源极/漏极，第一和第二源极/漏极间隔开并由衬底中的沟道区分隔开; 位于所述沟道区上的所述衬底顶表面上的栅电介质; 以及在所述栅极电介质的顶表面上的导电栅极; 以及栅极上的第一介电材料的介电柱; 以及介于第一和第二源极/漏极之间的第二介电材料的电介质层，介电柱的侧壁与电介质层直接物理接触，该介电柱不具有内部应力或不同于内部应力的内部应力 电介质层。
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