利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

42 条记录 (耗时 0.017 秒)

    Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions
    23.
    发明授权
    Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions 有权
    用于制造包括非易失性存储单元和具有浸水结的LV晶体管的电子器件的方法

    公开(公告)号：US06396101B2

    公开(公告)日：2002-05-28

    申请号：US09836590

    申请日：2001-04-16

    申请人： Matteo Patelmo ,  Giovanna Dalla Libera ,  Nadia Galbiati ,  Bruno Vajana

    发明人： Matteo Patelmo ,  Giovanna Dalla Libera ,  Nadia Galbiati ,  Bruno Vajana

    IPC分类号： H01L29788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

    摘要： A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

    摘要翻译： 一种用于制造具有水银结的电子器件（诸如存储器单元和LV晶体管）的方法，其包括：沉积多层硅的上层; 限定上层，获得第一区域上的浮栅区域，在衬底的第二区域上的LV栅极区域和衬底的第一和第三区域上的未定义区域; 在浮动栅极区域侧向形成第一单元源区域; 在LV栅极区域侧向形成LV源极和漏极区域; 在LV源极和漏极区域，LV栅极区域和未限定部分上形成硅化物层; 在所述第三区域上限定HV栅极区域，以及在所述第一区域上选择栅极区域; 在选择栅极区域横向形成源极区域，以及横向于HV栅极区域的源极和漏极区域。

    Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions
    24.
    发明授权
    Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions 有权
    用于制造具有浮动栅极区域的尺寸控制的非易失性存储单元的工艺

    公开(公告)号：US06340828B1

    公开(公告)日：2002-01-22

    申请号：US09587377

    申请日：2000-06-01

    申请人： Giovanna Dalla Libera ,  Bruno Vajana ,  Matteo Patelmo

    发明人： Giovanna Dalla Libera ,  Bruno Vajana ,  Matteo Patelmo

    IPC分类号： H01L29778

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42324

    摘要： A manufacturing process including forming a first insulating region on top of an active area; forming a tunnel region laterally to the first insulating region; forming a floating gate region; sealing the floating gate region with an insulating region; forming a control gate region on top of the floating gate region; and forming conductive regions in the active area. The floating gate region is obtained by depositing and defining a semiconductor material layer through a floating gate mask. The floating gate mask has an opening with an internally delimiting side extending at a preset distance from a corresponding externally delimiting side of the mask, and the semiconductor material layer is removed laterally at the external and internal delimiting sides so that the tunnel area's length is defined, by the floating gate mask alone.

    摘要翻译： 一种制造方法，包括在有源区域的顶部形成第一绝缘区域; 在所述第一绝缘区域上横向形成隧道区域; 形成浮栅区域; 用绝缘区域密封浮动栅极区域; 在浮置栅极区域的顶部形成控制栅极区域; 以及在有源区域中形成导电区域。 通过通过浮栅掩模沉积和限定半导体材料层来获得浮栅区域。 浮栅掩模具有开口，其内部限定侧以距掩模的对应的外部限定侧延伸预定距离，并且半导体材料层在外部和内部限定侧横向移除，使得隧道区域的长度被限定 ，由浮动门口罩单独使用。

    Memory cell for EEPROM devices and corresponding fabricating process
    25.
    发明授权
    Memory cell for EEPROM devices and corresponding fabricating process 有权
    用于EEPROM器件的存储单元和相应的制造工艺

    公开(公告)号：US06320219B1

    公开(公告)日：2001-11-20

    申请号：US09576168

    申请日：2000-05-22

    申请人： Bruno Vajana ,  Carlo Cremonesi ,  Roberta Bottini ,  Giovanna Dalla Libera

    发明人： Bruno Vajana ,  Carlo Cremonesi ,  Roberta Bottini ,  Giovanna Dalla Libera

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.

    摘要翻译： 形成在具有第一导电类型的半导体材料基板上的EEPROM型存储单元包括具有第二导电类型的漏极区域，并且在包括薄隧道氧化物区域的栅极氧化物区域的一侧延伸。 存储单元还包括具有第二导电类型的电连续性区域，横向形成在薄隧道氧化物区域下方，并且部分地与漏极区域重叠。 通过以预定的倾斜角度的注入产生电连续性的区域。

    Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions
    26.
    发明授权
    Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions 有权
    用于制造包括非易失性存储单元和具有浸水结的LV晶体管的电子器件的方法

    公开(公告)号：US06281077B1

    公开(公告)日：2001-08-28

    申请号：US09392937

    申请日：1999-09-09

    申请人： Matteo Patelmo ,  Giovanna Dalla Libera ,  Nadia Galbiati ,  Bruno Vajana

    发明人： Matteo Patelmo ,  Giovanna Dalla Libera ,  Nadia Galbiati ,  Bruno Vajana

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529

    摘要： A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

    摘要翻译： 一种用于制造具有水银结的电子器件（诸如存储器单元和LV晶体管）的方法，其包括：沉积多层硅的上层; 限定上层，获得第一区域上的浮栅区域，在衬底的第二区域上的LV栅极区域和衬底的第一和第三区域上的未定义区域; 在浮动栅极区域侧向形成第一单元源区域; 在LV栅极区域侧向形成LV源极和漏极区域; 在LV源极和漏极区域，LV栅极区域和未限定部分上形成硅化物层; 在所述第三区域上限定HV栅极区域，以及在所述第一区域上选择栅极区域; 在选择栅极区域横向形成源极区域，以及横向于HV栅极区域的源极和漏极区域。

    Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors
    28.
    发明授权
    Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors 有权
    用于制造具有非盐化非易失性存储单元，非水银高压晶体管和水银结LV晶体管的电子器件的方法

    公开(公告)号：US06573130B1

    公开(公告)日：2003-06-03

    申请号：US09426094

    申请日：1999-10-22

    申请人： Matteo Patelmo ,  Giovanna Dalla Libera ,  Nadia Galbiati ,  Bruno Vajana

    发明人： Matteo Patelmo ,  Giovanna Dalla Libera ,  Nadia Galbiati ,  Bruno Vajana

    IPC分类号： H01L218238

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

    摘要： A process that provides for the manufacture of LV transistors with salicidated junctions on first areas of a substrate, HV transistors on second areas, and memory cells on third areas. The process includes forming LV oxide regions and LV gate regions on the first areas, HV oxide regions on the second areas, selection oxide regions, tunnel oxide regions, and matrix oxide regions on the third areas; forming floating gate regions and insulating regions on the tunnel oxide regions and the matrix oxide regions; forming first LV source and drain regions laterally to the LV gate regions; forming silicide regions on the first source and drain regions and on the LV gate regions; forming semiconductor material regions completely covering the second and third areas; and at the same time forming HV gate regions on the HV oxide regions, forming selection gate regions on the selection oxide regions, and forming control gate regions on the insulating regions through shaping of the semiconductor material regions.

    摘要翻译： 提供在衬底的第一区域上制造具有盐渍结的LV晶体管，第二区域上的HV晶体管和第三区域上的存储器单元的方法。 该工艺包括在第一区域上形成LV氧化物区域和LV栅极区域，在第三区域上形成第二区域上的HV氧化物区域，选择氧化物区域，隧道氧化物区域和基质氧化物区域; 在隧道氧化物区域和基体氧化物区域上形成浮栅区域和绝缘区域; 在LV栅极区域上横向形成第一LV源极和漏极区域; 在第一源极和漏极区域以及LV栅极区域上形成硅化物区域; 完全覆盖第二和第三区域的半导体材料区域; 同时在HV氧化物区域上形成HV栅极区域，在选择氧化物区域上形成选择栅极区域，并且通过半导体材料区域的成形在绝缘区域上形成控制栅极区域。

    Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information
    29.
    发明授权
    Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information 有权
    一种用于制造半导体存储器件的方法，包括大容量存储单元和用于存储预留信息的屏蔽存储单元

    公开(公告)号：US06548354B2

    公开(公告)日：2003-04-15

    申请号：US09796757

    申请日：2001-02-28

    申请人： Roberta Bottini ,  Giovanna Dalla Libera ,  Bruno Vajana ,  Federico Pio

    发明人： Roberta Bottini ,  Giovanna Dalla Libera ,  Bruno Vajana ,  Federico Pio

    IPC分类号： H01L21336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11558

    摘要： A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

    摘要翻译： 半导体存储器件的制造方法包括双重多晶硅级非易失性存储单元和同一半导体材料芯片中的屏蔽单个多晶硅级非易失性存储单元。 第一存储单元包括MOS晶体管，其具有叠加并分别形成在第一和第二导电材料层中的第一栅电极和第二栅电极。 第二存储单元被屏蔽材料层屏蔽，以防止存储在第二存储单元中的信息可从外部访问。 第二存储单元包括具有通过第一导电材料层与第一单元的第一栅电极同时形成的浮栅的MOS晶体管。 屏蔽材料层通过第二层导电材料的定义形成。

    Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells
    30.
    发明授权
    Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells 有权
    用于制造FLOTOX EEPROM非自动对准半导体存储器单元的简化DSCP过程

    公开(公告)号：US06479347B1

    公开(公告)日：2002-11-12

    申请号：US09419617

    申请日：1999-10-14

    申请人： Giovanna Dalla Libera ,  Bruno Vajana

    发明人： Giovanna Dalla Libera ,  Bruno Vajana

    IPC分类号： H01L21336

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： A simplified DSCP process makes non-self-aligned floating gate semiconductor memory cells of the FLOTOX EEPROM type as incorporated to a cell matrix having control circuitry associated therewith, wherein each cell has a selection transistor associated therewith. The process includes at least the following steps: growing or depositing a gate dielectric layer of the selection transistor and the cell; tunnel masking to define the tunnel area with a dedicated etching step for cleaning the semiconductor surface; growing the tunnel oxide; depositing and doping the first polysilicon layer poly1. The process further comprises the following steps: poly1 masking to fully define the floating gate of the cell, the poly1 being removed from the area of the selection transistor during this step; depositing or growing the interpoly dielectric and forming tunnel oxide and interpoly dielectric; depositing or growing the interpoly dielectric and forming the overall gate dielectric of the selection transistor, which will therefore consist of the stacked interpoly dielectric and gate dielectric as previously grown or deposited; matrix masking to only remove interpoly dielectric from the circuitry; depositing and doping a second polysilicon layer poly2; masking the second layer of polysilicon to define the control and selection gate; poly etching in the matrix as far down as the intermediate dielectric layer; poly etching in the circuitry the whole short-circuited poly1/poly2 stack.

    摘要翻译： 简化的DSCP处理使得FLOTOX EEPROM类型的非自对准浮置半导体存储器单元并入具有与其相关联的控制电路的单元矩阵，其中每个单元具有与其相关联的选择晶体管。 该方法至少包括以下步骤：生长或沉积选择晶体管和电池的栅介电层; 隧道掩蔽以通过用于清洁半导体表面的专用蚀刻步骤限定隧道区域; 生长隧道氧化物; 沉积和掺杂第一多晶硅层poly1。 该方法还包括以下步骤：poly1掩蔽以完全限定电池的浮置栅极，在该步骤期间，poly1从选择晶体管的区域中去除; 沉积或生长多层电介质并形成隧道氧化物和互聚电介质; 沉积或生长多晶硅电介质并形成选择晶体管的总体栅极电介质，因此其将由先前生长或沉积的堆叠的多晶硅间介质和栅极电介质构成; 矩阵掩蔽只能从电路中去除多晶硅电介质; 沉积和掺杂第二多晶硅层poly2; 掩蔽第二层多晶硅以限定控制和选择门; 在与中间介电层一样远的矩阵中进行多层蚀刻; 整个电路中多晶硅刻蚀了整个短路的poly1 / poly2叠层。