公开(公告)号：US20120125679A1

公开(公告)日：2012-05-24

申请号：US13032653

申请日：2011-02-23

Applicant: YUNG-CHIEH CHEN ,  CHENG-HSIEN LEE ,  PO-CHUAN HSIEH ,  SHOU-KUO HSU ,  SHIN-TING YEN

Inventor： YUNG-CHIEH CHEN ,  CHENG-HSIEN LEE ,  PO-CHUAN HSIEH ,  SHOU-KUO HSU ,  SHIN-TING YEN

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K1/116

Abstract: A printed circuit board includes an insulating board, a pair of differential vias, and a number of wiring layers. A pair of via holes extends through opposite surfaces of the insulating board. The differential vias correspond to the pair of via holes. Each differential via includes a metal plated barrel and two via capture pads. The plated barrel is plated on the inner surface of the respective via hole, and terminates at each of the two opposite surfaces of the insulating board. The via capture pads are formed on the opposite surfaces of the insulating board around the openings of the via hole, and are electrically connected to the plated barrel. The wiring layers are arranged in the insulating board, and each define a clearance hole surrounding all of the via capture pads.

Abstract translation: 印刷电路板包括绝缘板，一对差动通孔和多个布线层。 一对通孔延伸穿过绝缘板的相对表面。 差分过孔对应于一对通孔。 每个差分通孔包括一个金属电镀桶和两个通孔捕获垫。 电镀桶被镀在相应通孔的内表面上，并且终止于绝缘板的两个相对表面的每一个。 通孔捕获垫形成在绝缘板的围绕通孔的开口的相对表面上，并且电连接到电镀桶。 布线层布置在绝缘板中，并且每个限定围绕所有通孔捕获垫的间隙孔。

公开(公告)号：US20110301922A1

公开(公告)日：2011-12-08

申请号：US12958397

申请日：2010-12-02

Applicant: WEN-LAING TSENG ,  CHENG-HSIEN LEE ,  SHEN-CHUN LI ,  YU-CHANG PAI ,  SHOU-KUO HSU

Inventor： WEN-LAING TSENG ,  CHENG-HSIEN LEE ,  SHEN-CHUN LI ,  YU-CHANG PAI ,  SHOU-KUO HSU

IPC: G06F17/50 ,  G06F17/10

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: A simulation system for producing equivalent circuits reads data corresponding to a tabular W element format in a storage device, and adds data of the tabular W element format file using interpolation algorithm. A frequency-dependent transmission matrix is transformed into an N-port network matrix describing electrical properties of a multi-input and multi-output network. An N-port network matrix is transformed into a S-parameter matrix. A range of frequency of a s-parameter is determined and numbers of pole-residue, times for recursion and durable maximum system errors in the equivalent circuit is also determined. A a vector fitting algorithm is performed and a rational function matrix composed with s-parameters is produced, to produce a general SPICE equivalent circuit based on the generated rational function matrix.

Abstract translation: 用于产生等效电路的仿真系统在存储装置中读取对应于表格W元素格式的数据，并且使用插值算法来添加表格W元素格式文件的数据。 频率依赖传输矩阵被转换成描述多输入和多输出网络的电特性的N端口网络矩阵。 将N端口网络矩阵转换为S参数矩阵。 确定s参数的频率范围，并确定等效电路中极点残差，递归次数和持久最大系统误差的数量。 执行向量拟合算法，并产生由s参数组成的有理函数矩阵，以产生基于生成的有理函数矩阵的一般SPICE等效电路。

公开(公告)号：US20110231175A1

公开(公告)日：2011-09-22

申请号：US12978417

申请日：2010-12-24

Applicant: CHENG-HSIEN LEE ,  SHOU-KUO HSU

Inventor： CHENG-HSIEN LEE ,  SHOU-KUO HSU

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: In an electronic device and a method of generating composite electrical signals, a plurality of post-processing software is installed. An output file, which comprises times and voltages of data points that represent an electrical signal, of an electronic circuit simulation software is loaded, and is read using the installed post-processing software. A time interval of outputs of the electrical signal is obtained by selecting an output type of the electrical signal. The worst bit combination of outputs of the electrical signal is analyzed according to the times, the voltage, and the time interval, and a composite electrical signal is generated according to the worst bit combination.

Abstract translation: 在电子设备和产生复合电信号的方法中，安装了多个后处理软件。 加载电子电路仿真软件的包括代表电信号的数据点的时间和电压的输出文件，并使用安装的后处理软件进行读取。 通过选择电信号的输出类型来获得电信号的输出的时间间隔。 根据时间，电压和时间间隔分析电信号输出的最差位组合，并根据最差位组合生成复合电信号。

公开(公告)号：US20110066764A1

公开(公告)日：2011-03-17

申请号：US12606120

申请日：2009-10-26

Applicant: SHOU-KUO HSU ,  CHENG-HSIEN LEE

Inventor： SHOU-KUO HSU ,  CHENG-HSIEN LEE

IPC: G06F3/00

CPC classification number: G06F13/4282

Abstract: A system for selecting high speed serial signals includes a loading module, a layout selecting module, a data processing module, and an output module. The loading module reads a chip package length file; a layout selecting module reads a layout file and selects high speed serial signals preset by a user; the data processing module selects pins information of a start chip and a terminal chip transmit the selected high speed serial signals and finds the chip package length information, and analyzes interrupt points of the layout character from the start chip and outputs the chip package length information of the start chip, the layout length information, and the chip package length information of the terminal chip in sequence to the output module, to convert into a table and displays the table via a display device.

Abstract translation: 用于选择高速串行信号的系统包括加载模块，布局选择模块，数据处理模块和输出模块。 加载模块读取芯片封装长度文件; 布局选择模块读取布局文件并选择用户预设的高速串行信号; 数据处理模块选择起始芯片的引脚信息和终端芯片发送所选择的高速串行信号，并找到芯片封装长度信息，并从启动芯片分析布局字符的中断点，并输出芯片封装长度信息 开始芯片，布局长度信息，以及终端芯片的芯片封装长度信息顺序地输出到输出模块，转换成表格并通过显示装置显示表格。

公开(公告)号：US20120066660A1

公开(公告)日：2012-03-15

申请号：US13092966

申请日：2011-04-24

Applicant: HSIAO-YUN SU ,  YING-TSO LAI ,  CHENG-HSIEN LEE

Inventor： HSIAO-YUN SU ,  YING-TSO LAI ,  CHENG-HSIEN LEE

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/10

Abstract: In a method of managing process factors that influence electrical properties of printed circuit boards (PCBs), n process factors are arranged in an order according to different influence to one kind of electrical property of the PCBs. The different influence is determined by first experiments designed using the Taguchi method. M process factors that have important influence to the electrical property are obtained from the n process factors according to the order to design second experiments. A computing formula for the electrical property is fitted using the m process factors according to simulated results of the second experiments, and a variation range of each of the m process factors is computed according to the computing formula.

Abstract translation: 在管理影响印刷电路板（PCB）的电性能的工艺因素的方法中，根据对PCB的一种电性能的不同影响，n个工艺因素按顺序排列。 不同的影响由使用田口方法设计的第一个实验确定。 对电性能有重要影响的M个工艺因素根据设计第二个实验的顺序从n个工艺因素中获得。 根据第二次实验的模拟结果，使用m个工艺因子拟合电性能的计算公式，并根据计算公式计算每个m个工艺因子的变化范围。

公开(公告)号：US20120026902A1

公开(公告)日：2012-02-02

申请号：US12961906

申请日：2010-12-07

Applicant: YING-TSO LAI ,  SHI-PIAO LUO ,  CHENG-HSIEN LEE

Inventor： YING-TSO LAI ,  SHI-PIAO LUO ,  CHENG-HSIEN LEE

IPC: H04L12/26

CPC classification number: G06F17/5081 ,  G06F2217/82

Abstract: A computing device and a method reads a circuit board layout file from a storage device, and selects a first signal transmission line from circuit board layout file as a target line. The computing device and method computes a distance between the target line and the aggressor line corresponding to each unit sample length. If the distance is more than or equal to a height of a sample region, the computing device and method defines the height of the sample region as a crosstalk space between the target line and the aggressor line corresponding to a unit sample length. Otherwise, if the distance is less than the height of the sample region, the computing device and method defines the distance as the crosstalk space between the target line and the aggressor line corresponding to the unit sample length.

Abstract translation: 计算装置和方法从存储装置读取电路板布局文件，并从电路板布局文件中选择第一信号传输线作为目标线。 计算装置和方法计算目标线与对应于每个单位样本长度的侵略线之间的距离。 如果距离大于或等于样本区域的高度，则计算设备和方法将样本区域的高度定义为目标线与对应于单位样本长度的侵略线之间的串扰空间。 否则，如果距离小于样本区域的高度，则计算装置和方法将该距离定义为对应于单位样本长度的目标线与侵略线之间的串扰空间。

公开(公告)号：US20120229997A1

公开(公告)日：2012-09-13

申请号：US13050954

申请日：2011-03-18

Applicant: HSIAO-YUN SU ,  YUNG-CHIEH CHEN ,  CHENG-HSIEN LEE

Inventor： HSIAO-YUN SU ,  YUNG-CHIEH CHEN ,  CHENG-HSIEN LEE

IPC: H05K7/00

CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K2201/09718

Abstract: A printed circuit board includes first and second transmission lines connected to a first high speed differential signal control chip, third and fourth transmission lines connected to a second high speed differential signal control chip, and fifth and sixth transmission lines connected to a connector pad. To have the first high speed differential signal control chip communicate with the connector pad, the first transmission line is connected to the fifth transmission line through a first connection component, and the second transmission line is connected to the sixth transmission line through a second connection component. To have the second speed differential signal control chip communicate with the connector pad, the third transmission line is connected to the fifth transmission line through the first connection component, and the fourth transmission line is connected to the sixth transmission line through the second connection component.

Abstract translation: 印刷电路板包括连接到第一高速差分信号控制芯片的第一和第二传输线，连接到第二高速差分信号控制芯片的第三和第四传输线以及连接到连接器焊盘的第五和第六传输线。 为了使第一高速差分信号控制芯片与连接器焊盘通信，第一传输线通过第一连接部件连接到第五传输线，并且第二传输线通过第二连接部件连接到第六传输线 。 为了使第二速度差分信号控制芯片与连接器焊盘通信，第三传输线通过第一连接部件连接到第五传输线，并且第四传输线通过第二连接部件连接到第六传输线。

公开(公告)号：US20120110540A1

公开(公告)日：2012-05-03

申请号：US13094807

申请日：2011-04-26

Applicant: HSIAO-YUN SU ,  YING-TSO LAI ,  CHENG-HSIEN LEE

Inventor： HSIAO-YUN SU ,  YING-TSO LAI ,  CHENG-HSIEN LEE

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5036 ,  G06F17/5068 ,  G06F2217/08

Abstract: In a method of optimizing parameters of electronic components on printed circuit boards (PCBs), a first experiment table for m variables of one type of parameter of P electronic components on a PCB is designed using n values of each variable and the RSM. P EHs of each first experiment are obtained by simulating, and P EH empirical formulas are computed according to the P EHs. A second experiment table for the m variables is designed using n′ values of each variable and the full factorial design, and P EHs of each second experiment are computed using the P EH empirical formulas. Experiments, all the P EHs of which are greater than 1, are filtered from the second experiment tables, and an average EH of each filtered experiment is computed to pick an experiment the average EH of which is the greatest. The values of the m variables in the picked experiment are considered as optimized.

Abstract translation: 在印刷电路板（PCB）上优化电子部件参数的方法中，使用每个变量和RSM的n个值设计PCB上P电子部件的一种类型参数的m个变量的第一个实验表。 通过模拟获得每个第一个实验的P EH，并且根据P EH计算P EH经验公式。 使用每个变量的n'值和全因子设计设计m个变量的第二个实验表，并且使用P EH经验公式计算每个第二个实验的P EH。 从第二个实验表中筛选出所有P EH大于1的实验，并计算每个滤波实验的平均EH，以选择其平均EH最大的实验。 所选实验中的m个变量的值被认为是优化的。

公开(公告)号：US20110161259A1

公开(公告)日：2011-06-30

申请号：US12649359

申请日：2009-12-30

Applicant: CHENG-HSIEN LEE

Inventor： CHENG-HSIEN LEE

IPC: G06F15/18 ,  G06F15/16

CPC classification number: G06K9/6257

Abstract: A method for simplification of a matrix based boosting algorithm divides a feature set comprising a plurality of feature data into several subsets, and assigns a number to each subset. The method selects a plurality of number groups including N subsets randomly. The method further computes a value by boosting algorithm according to each of the number groups for obtaining an acceptable false positive value.

Abstract translation: 一种用于简化基于矩阵的增强算法的方法将包括多个特征数据的特征集划分成若干子集，并为每个子集分配一个数字。 该方法随机选择包括N个子集的多个数字组。 该方法通过根据每个数组来提升算法来进一步计算值以获得可接受的假正值。

公开(公告)号：US20130222082A1

公开(公告)日：2013-08-29

申请号：US13564768

申请日：2012-08-02

Applicant: PO-CHUAN HSIEH ,  YING-TSO LAI ,  CHENG-HSIEN LEE

Inventor： PO-CHUAN HSIEH ,  YING-TSO LAI ,  CHENG-HSIEN LEE

IPC: H04B3/14

CPC classification number: H04B3/14

Abstract: An equalizer includes a first delay module, a second delay module, a first amplitude module, a second amplitude module, and a combining unit. The first delay module receives a first signal and delays the first received signal for a preset period, and the first amplitude module transfers the first delayed signal to transmit a first weighted signal with a first peak amplitude. Similarly, the second delay module receives the first delayed signal and delays the second received signal for the preset period, and the second amplitude module transfers the second delayed signal to transmit a second weighted signal with a second peak amplitude. The combining unit combines an input signal and the first and the second weighted signals together to generate an equalized signal.

Abstract translation: 均衡器包括第一延迟模块，第二延迟模块，第一振幅模块，第二振幅模块和组合单元。 第一延迟模块接收第一信号并将第一接收信号延迟预设周期，并​​且第一幅度模块传送第一延迟信号以发送具有第一峰值幅度的第一加权信号。 类似地，第二延迟模块接收第一延迟信号并将第二接收信号延迟预设周期，并​​且第二幅度模块传送第二延迟信号以发送具有第二峰值振幅的第二加权信号。 组合单元将输入信号和第一和第二加权信号组合在一起以产生均衡的信号。