公开(公告)号：US20180228019A1

公开(公告)日：2018-08-09

申请号：US15428865

申请日：2017-02-09

Applicant: Cray Inc.

Inventor： Andy Becker ,  Hyunjun Kim ,  Shawn Utz ,  Paul Wildes

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  G06F17/50

CPC classification number: H05K1/0251 ,  G06F17/5009 ,  G06F17/5072 ,  G06F17/5081 ,  H05K1/024 ,  H05K1/112 ,  H05K1/113 ,  H05K1/116 ,  H05K3/0005 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09781

Abstract: The various structures forming communication paths on a printed circuit board can create several undesired effects, especially when high frequency signals are considered. Non-functional pads created during the manufacturing process have the potential to create an undesired effect, but when the overall collection of non-functional pads are carefully configured, an optimized communication path can be formed. More specifically, by selectively removing some collection of the non-functional pads, the high frequency characteristics of the communication paths can be optimized.

公开(公告)号：US09859603B2

公开(公告)日：2018-01-02

申请号：US14762321

申请日：2014-01-08

Applicant: NEC Corporation

Inventor： Kazuhiro Kashiwakura

IPC: H01P3/08 ,  H05K1/02 ,  H01P3/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H01P3/082 ,  H01P3/026 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09718 ,  Y10T29/49167

Abstract: A printed wiring board is provided with a wiring layer, a first ground layer, a second ground layer, a grounding through-hole, a signal through-hole, a first clearance, and a second clearance. The wiring layer has a signal line. The first ground layer has a first ground plane. The second ground layer is positioned between the wiring layer and the first ground layer and has a second ground plane. The grounding through-hole passes through the wiring layer, the first ground layer, and the second ground layer and is connected to the second ground plane. The signal through-hole passes through the wiring layer, the first ground layer, and the second ground layer and is connected to the signal line. The first clearance is formed in the first ground layer, is positioned in the vicinity of the signal through-hole and the grounding through-hole, and separates the first ground plane from the signal through-hole and the grounding through-hole. The second clearance is formed in the second ground layer, is positioned in the vicinity of the signal through-hole, and separates the second ground plane from the signal through-hole.

公开(公告)号：US20160150633A1

公开(公告)日：2016-05-26

申请号：US14947091

申请日：2015-11-20

Applicant: Amphenol Corporation

Inventor： Marc B. Cartier, JR.

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11 ,  H01R43/20

CPC classification number: H05K1/0222 ,  H01R43/205 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/07 ,  H05K2201/09063 ,  H05K2201/09318 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/097 ,  H05K2201/09718 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10189

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.

Abstract translation: 印刷电路板包括多个层，包括附着层和布线层; 以及形成在所述多个层中的通孔图案，所述通孔图案中的每一个包括：形成差分信号对的双直径第一和第二信号通孔，所述第一和第二信号通孔被配置为接纳连接器的信号导体的接触尾部; 与第一和第二信号通孔中的每一个相邻的双直径地面阴影通孔，其中双直径阴影接地通孔相对于双直径第一和第二信号通孔具有反向直径构型; 以及配置为接受连接器的接地导体的接触尾部的接地通孔。

公开(公告)号：US09265149B2

公开(公告)日：2016-02-16

申请号：US13442423

申请日：2012-04-09

Applicant: Kazuhiro Kashiwakura

Inventor： Kazuhiro Kashiwakura

IPC: H05K3/00 ,  H01R43/00 ,  H05K3/36 ,  H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09618 ,  H05K2201/09718 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: A printed wiring board comprises ground layers stacked via insulator(s); a first through hole; second through holes ; and signal wirings each extending from the first through hole through the clearance between predetermined ones of the ground layers, disposed between predetermined second through holes of the second through holes. Each of first clearances in the ground layers neighboring layer in which the signal wiring is disposed has an outline that a distance between the first through hole and outline of the first clearance is minimum of the signal wiring. Each of second clearances in the ground layers not adjacent to the signal wiring has an outline formed outside a circle connecting each center of second through holes centering the first signal through hole, such that outline of second clearance does not contact with the second through holes.

Abstract translation: 印刷电路板包括通过绝缘体堆叠的接地层; 第一个通孔; 第二通孔; 以及信号布线，其各自从第一通孔延伸穿过位于第二通孔的预定第二通孔之间的预定接地层之间的间隙。 其中布置信号布线的地层相邻层中的每个第一间隙具有第一通孔之间的距离和第一间隙的轮廓线是信号布线最小的轮廓。 与信号线不相邻的接地层中的每个第二间隙具有形成在连接第一通孔的中心的第二通孔的圆周外的轮廓，使得第二间隙的轮廓不与第二通孔接触。

公开(公告)号：US09236189B2

公开(公告)日：2016-01-12

申请号：US14014773

申请日：2013-08-30

Applicant: SAMHWA CAPACITOR CO., LTD.

Inventor： Young Joo Oh ,  Jung Rag Yoon ,  Kyung Min Lee ,  Young Min Yoo

IPC: H01G4/38 ,  H01G4/40 ,  H01G2/06 ,  H05K1/02 ,  H05K1/11 ,  H05K3/30 ,  H05K3/46

CPC classification number: H01G4/38 ,  H01G2/06 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/306 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09718 ,  H05K2201/1034 ,  Y02T10/7022

Abstract: A direct current (DC) link capacitor module includes a printed circuit board (PCB) formed by sequentially disposing a first electrode substrate, an insulation substrate, a second electrode substrate, a third electrode substrate; a plurality of DC link capacitors connected in parallel to each of the first electrode substrate and the second electrode substrate; a plurality of first Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the DC link capacitors; and a plurality of second Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the first Y-capacitors, thereby achieving a miniaturization and facilitating a fabrication by connecting the plurality of DC link capacitors using the PCB.

Abstract translation: 直流（DC）链路电容器模块包括通过顺序地布置第一电极基板，绝缘基板，第二电极基板，第三电极基板形成的印刷电路板（PCB） 与第一电极基板和第二电极基板中的每一个并联连接的多个DC链路电容器; 多个第一Y电容器，与第一电极基板和第三电极基板中的每一个串联连接，并联连接到直流链路电容器; 以及与第一电极基板和第三电极基板中的每一个串联连接并与第一Y电容器并联连接的多个第二Y电容器，从而实现小型化，并且通过将多个DC链路 电容使用PCB。

公开(公告)号：US09226399B2

公开(公告)日：2015-12-29

申请号：US12952234

申请日：2010-11-23

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H01G4/00 ,  H05K1/16 ,  H05K1/18 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A wiring board with built-in capacitors includes a core substrate, and a high dielectric sheet including a lower electrode layer, an upper electrode layer and a dielectric layer, the dielectric layer made of a sintered ceramic body and sandwiched between the lower electrode layer and the upper electrode layer, the lower electrode layer and/or the upper electrode layer being partitioned into multiple electrodes such that the high dielectric sheet has multiple capacitors. The lower electrode layer and/or the upper electrode layer is connected to a ground line and the other one of the lower electrode layer and the upper electrode layer is connected to a power line such that the capacitors are electrically connected in parallel.

Abstract translation: 具有内置电容器的布线板包括芯基板和包括下电极层，上电极层和电介质层的高电介质层，所述电介质层由烧结陶瓷体制成并夹在下电极层和 上电极层，下电极层和/或上电极层分隔成多个电极，使得高电介质片具有多个电容器。 下电极层和/或上电极层连接到接地线，并且下电极层和上电极层中的另一个连接到电源线，使得电容器并联电连接。

公开(公告)号：US20150250055A1

公开(公告)日：2015-09-03

申请号：US14194278

申请日：2014-02-28

Applicant: FUJITSU LIMITED

Inventor： Yasuo HIDAKA

IPC: H05K1/11 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/116 ,  H05K1/0225 ,  H05K1/0251 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09727 ,  H05K2201/09845 ,  Y10T29/49165

Abstract: A circuit may include a signal path, a first layer including the signal path, and a second layer including the signal path. The circuit may additionally include a path via having a signal-path via location and configured to connect the signal path at the first layer with the signal path at the second layer. The circuit may also include a ground plane associated with the first layer. The ground plane may have a ground-plane location that corresponds to the signal-path via location. The ground plane may also include an asymmetrical cutout portion that extends away from the ground-plane location on a first side of the ground plane that is opposite a second side of the ground plane that corresponds with a side of the first layer where the path via interfaces with the signal path at the first layer.

Abstract translation: 电路可以包括信号路径，包括信号路径的第一层，以及包括信号路径的第二层。 电路还可以包括具有经由位置的信号路径的路径通路，并被配置为将第一层处的信号路径与第二层处的信号路径连接。 电路还可以包括与第一层相关联的接地平面。 接地平面可以具有对应于信号路径经过位置的接地平面位置。 接地平面还可以包括不对称的切口部分，其在接地平面的第一侧上远离接地平面位置延伸，该接地平面位于接地平面的与第一层的一侧相对的第二侧，其中通路 与第一层的信号路径接口。

公开(公告)号：US20150114706A1

公开(公告)日：2015-04-30

申请号：US14511397

申请日：2014-10-10

Applicant: Curtiss-Wright Controls, Inc.

Inventor： Michael Rose ,  Robert Sullivan

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/20 ,  H05K3/4038 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/1059

Abstract: A circuit board comprises a plurality of layers, first and second reference conductive vias extending in a vertical direction through at least a portion of the plurality of layers, first and second signal conductive vias extending in the vertical direction between and spaced apart in a horizontal direction from the first and second reference conductive vias through at least a portion of the plurality of layers, and a dielectric region extending in the vertical direction between the first and second signal conductive vias. An air via extends in the vertical direction through the dielectric region between the first and second signal conductive vias. An anti-pad extends in the horizontal direction between the first and second reference conductive vias and surrounding in the horizontal direction the first and second signal conductive vias, the air via, and the dielectric region.

Abstract translation: 电路板包括多个层，第一和第二参考导电通孔在垂直方向上延伸穿过多个层的至少一部分，第一和第二信号导电通孔在垂直方向上延伸并且在水平方向间隔开 从所述第一和第二参考导电通孔穿过所述多个层的至少一部分，以及在所述第一和第二信号导电通孔之间沿垂直方向延伸的电介质区域。 空气通道在垂直方向上延伸穿过第一和第二信号导电通孔之间的电介质区域。 反焊盘在第一和第二参考导电通孔之间沿水平方向延伸，并且在水平方向上包围第一和第二信号导电通孔，空气通孔和电介质区域。

公开(公告)号：US08975525B2

公开(公告)日：2015-03-10

申请号：US13614314

申请日：2012-09-13

Applicant: Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

Inventor： Kevin Bills ,  Mahesh Bohra ,  Jinwoo Choi ,  Tae Hong Kim ,  Rohan Mandrekar

IPC: H05K1/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/144 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09718 ,  H05K2201/10734 ,  Y10T29/49124 ,  Y10T29/49151 ,  H01L2924/00

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract translation: 多层互连衬底具有至少两个间隔开的金属层，每个金属层上具有导电焊盘。 在金属层之间放置两种不同类型的绝缘层。 这种放置使得两种不同类型的绝缘层中的一种被放置在导电焊盘之间，另一种类型的绝缘层被放置在两个间隔开的金属层之间。

公开(公告)号：US20140326495A1

公开(公告)日：2014-11-06

申请号：US14240960

申请日：2012-08-27

Applicant: Jose Ricardo Paniagua

Inventor： Jose Ricardo Paniagua

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/10 ,  H05K3/00

CPC classification number: H05K1/116 ,  G06F17/5081 ,  G06F2217/82 ,  H05K1/0225 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/10 ,  H05K3/42 ,  H05K2201/0784 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/09718 ,  H05K2201/09727 ,  H05K2203/0207 ,  H05K2203/0242 ,  Y10T29/49165

Abstract: A printed circuit board for carrying high frequency signals. Conducting structures of the printed circuit board are shaped within breakout regions to limit impedance discontinuities in the signal paths between vias and conductive traces within the printed circuit board. Values of parameters of traces or anti-pads, for example, may be adjusted to provide a desired impedance. The specific values selected as part of designing a printed circuit board may match the impedance of the breakout region to that of the via. The parameters for which values are selected may include the trace width, thickness, spacing, length over an anti-pad or angle of exit from the breakout region.

Abstract translation: 用于承载高频信号的印刷电路板。 印刷电路板的导电结构在突出区域内成形，以限制印刷电路板内的通孔和导电迹线之间的信号路径中的阻抗不连续性。 痕迹或抗焊盘参数的值可以被调整以提供所需的阻抗。 选择作为设计印刷电路板的一部分的具体值可以将突破区域的阻抗与通孔的阻抗匹配。 选择值的参数可以包括迹线宽度，厚度，间隔，防焊盘上的长度或从断裂区域的出口角度。