公开(公告)号：US6051473A

公开(公告)日：2000-04-18

申请号：US755222

申请日：1996-11-22

申请人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju ,  Don Draper

发明人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju ,  Don Draper

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/768 ,  H01L29/417

CPC分类号： H01L29/66606 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/66575 ,  H01L29/66628 ,  H01L21/2257 ,  H01L29/66545

摘要： A process in accordance with the invention enables the manufacturability of raised source-drain MOSFETs. In accordance with the invention, a raised source-drain material, having a window therein, is formed over the substrate. A gate oxide and window sidewall oxides are subsequently formed. Dopants are diffused into the substrate. A gate is formed within the window.

摘要翻译： 根据本发明的方法能够提高升高的源极 - 漏极MOSFET的可制造性。 根据本发明，在衬底上形成一个其中具有窗口的升高的源极 - 漏极材料。 随后形成栅极氧化物和窗口侧壁氧化物。 掺杂剂扩散到衬底中。 窗口内形成门。

公开(公告)号：US5854132A

公开(公告)日：1998-12-29

申请号：US346041

申请日：1994-11-29

申请人： Shekhar Pramanick ,  Scott Luning ,  Jonathon Fewkes

发明人： Shekhar Pramanick ,  Scott Luning ,  Jonathon Fewkes

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/465

CPC分类号： G03F7/091 ,  H01L21/0276 ,  H01L21/32137

摘要： A method for patterning a polysilicon layer includes creating a TiN layer above an amorphous silicon (a-Si) layer forming a TiN/a-Si stack. The TiN/a-Si stack is formed above the polysilicon layer. The TiN layer serves as an ARC to reduce overexposure of the photoresist used to pattern the polysilicon layer, while the a-Si layer prevents contamination of the layer below the polysilicon layer.

摘要翻译： 用于图案化多晶硅层的方法包括在形成TiN / a-Si叠层的非晶硅（a-Si）层上方形成TiN层。 在多晶硅层上形成TiN / a-Si叠层。 TiN层用作ARC以减少用于图案化多晶硅层的光致抗蚀剂的过度曝光，而a-Si层防止多晶硅层下面的层被污染。

公开(公告)号：US5652447A

公开(公告)日：1997-07-29

申请号：US684920

申请日：1996-07-22

申请人： Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

发明人： Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C11/34 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.

摘要翻译： 具有降低的列泄漏电流的快闪EEPROM适当地包括以阵列布置的更均匀擦除次数的单元。 紧接在DDI注入步骤之后的中间n +注入适当地提供隧道区域中的增强的掺杂分布，这增加了发生FN隧道以擦除单元的速率，并且这增加阵列内的存储单元之间的FN隧穿速率的均匀性 。 热循环驱动中间n +植入物更深入隧道区域。 或者，可以相对于半导体衬底以相对大的角度执行n +注入，这改善了源极的隧道区域中的掺杂浓度。

公开(公告)号：US5482881A

公开(公告)日：1996-01-09

申请号：US403460

申请日：1995-03-14

申请人： Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

发明人： Jian Chen ,  Yuan Tang ,  Scott Luning ,  Salvatore F. Cagnina

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.

摘要翻译： 具有降低的列泄漏电流的快闪EEPROM适当地包括以阵列布置的更均匀擦除次数的单元。 紧接在DDI注入步骤之后的中间n +注入适当地提供隧道区域中的增强的掺杂分布，这增加了发生FN隧道以擦除单元的速率，并且这增加阵列内的存储单元之间的FN隧穿速率的均匀性 。 热循环驱动中间n +植入物更深入隧道区域。 或者，可以相对于半导体衬底以相对大的角度执行n +注入，这改善了源极的隧道区域中的掺杂浓度。

公开(公告)号：US08120120B2

公开(公告)日：2012-02-21

申请号：US12561685

申请日：2009-09-17

申请人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

发明人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

摘要翻译： 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

公开(公告)号：US20090283806A1

公开(公告)日：2009-11-19

申请号：US12121387

申请日：2008-05-15

申请人： Frank Bin YANG ,  Andrew M. WAITE ,  Scott Luning

发明人： Frank Bin YANG ,  Andrew M. WAITE ,  Scott Luning

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

摘要翻译： 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US07521380B2

公开(公告)日：2009-04-21

申请号：US11738828

申请日：2007-04-23

申请人： Andrew M. Waite ,  Scott Luning ,  Frank (Bin) Yang

发明人： Andrew M. Waite ,  Scott Luning ,  Frank (Bin) Yang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

摘要： A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.

摘要翻译： 提供了一种在半导体衬底上制造半导体器件的方法。 在半导体衬底上形成多个窄栅极间距晶体管（NPT）和宽栅极间距晶体管（WPT）。 NPT间隔开第一距离，并且WPT间隔开大于第一距离的第二距离。 沉积覆盖在NPT，WPT和半导体层上的第一应力衬垫层，沉积覆盖在第一应力衬垫层上的蚀刻停止层，并且沉积覆盖在蚀刻停止层上的第二应力衬垫层。 覆盖在WPT上的第二应力衬垫层的一部分被覆盖，并且去除覆盖在NPT上的第二应力衬垫层的暴露部分以露出蚀刻停止层的暴露部分。 去除覆盖在NPT上的蚀刻停止层的暴露部分。

公开(公告)号：US07279389B2

公开(公告)日：2007-10-09

申请号：US11280484

申请日：2005-11-16

申请人： Karla Romero ,  Thorsten Kammler ,  Scott Luning ,  Hans Van Meer

发明人： Karla Romero ,  Thorsten Kammler ,  Scott Luning ,  Hans Van Meer

IPC分类号： H01L21/336

CPC分类号： H01L21/32139 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

摘要： By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential for further device scaling of transistor devices requiring raised drain and source regions.

摘要翻译： 通过提供包括用于图案化栅电极结构的至少三个不同层的硬掩模层堆叠，可以实现随后的选择性外延生长工艺中复杂光刻所需的约束以及覆盖层完整性，从而提供进一步的潜力 晶体管器件的器件缩放需要高的漏极和源极区域。

公开(公告)号：US07176110B2

公开(公告)日：2007-02-13

申请号：US10862518

申请日：2004-06-07

申请人： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

发明人： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/66628 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/665

摘要： The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semiconductor region in a specified device region. In other embodiments, a common epitaxial growth process may be used for two or more different device regions and subsequently a selective oxidation process may be performed on selected device regions so as to precisely reduce the height of the previously epitaxially grown semiconductor regions in the selected areas.

摘要翻译： 可以对于不同的器件区域单独地调整极限比例的半导体器件中的外延生长的半导体区域的高度，因为可以执行两个或更多个外延生长步骤，其中外延生长掩模选择性地抑制在指定器件中形成半导体区域 地区。 在其它实施例中，公共外延生长工艺可以用于两个或更多个不同的器件区域，随后可以在所选择的器件区域上执行选择性氧化工艺，以便精确地降低所选区域中先前外延生长的半导体区域的高度 。

公开(公告)号：US07144786B2

公开(公告)日：2006-12-05

申请号：US10891996

申请日：2004-07-15

申请人： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

发明人： Ralf van Bentum ,  Scott Luning ,  Thorsten Kammler

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833

摘要： By using sidewall spacers adjacent to a gate electrode structure both as an epitaxial growth mask and an implantation mask, the complexity of a conventional process flow for forming raised drain and source regions may be significantly reduced, thereby reducing production costs and enhancing yield by lowering the defect rate.

摘要翻译： 通过使用与栅极电极结构相邻的侧壁间隔作为外延生长掩模和注入掩模，可以显着降低形成隆起的漏极和源极区域的常规工艺流程的复杂性，从而降低生产成本并通过降低 缺陷率。