公开(公告)号：US6051473A

公开(公告)日：2000-04-18

申请号：US755222

申请日：1996-11-22

申请人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju ,  Don Draper

发明人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju ,  Don Draper

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/768 ,  H01L29/417

CPC分类号： H01L29/66606 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/66575 ,  H01L29/66628 ,  H01L21/2257 ,  H01L29/66545

摘要： A process in accordance with the invention enables the manufacturability of raised source-drain MOSFETs. In accordance with the invention, a raised source-drain material, having a window therein, is formed over the substrate. A gate oxide and window sidewall oxides are subsequently formed. Dopants are diffused into the substrate. A gate is formed within the window.

摘要翻译： 根据本发明的方法能够提高升高的源极 - 漏极MOSFET的可制造性。 根据本发明，在衬底上形成一个其中具有窗口的升高的源极 - 漏极材料。 随后形成栅极氧化物和窗口侧壁氧化物。 掺杂剂扩散到衬底中。 窗口内形成门。

公开(公告)号：US5998272A

公开(公告)日：1999-12-07

申请号：US745475

申请日：1996-11-12

申请人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju

发明人： Emi Ishida ,  Scott Luning ,  Dong-Hyuk Ju

IPC分类号： H01L21/223 ,  H01L21/265 ,  H01L21/336

CPC分类号： H01L29/6653 ,  H01L21/223 ,  H01L21/2652 ,  H01L29/665 ,  H01L29/6659

摘要： A process in accordance with the invention minimizes the number of heat steps to which an source-drain extension region is exposed, thus minimizing source-drain extension region diffusion and allowing more precise control of source-drain extension region thickness over conventional processes. In accordance with the invention, spacers are formed abutting the gate and then heavily doped source and drain regions are formed. The gate and source and drain regions are silicided. The spacers are subsequently removed and source-drain extension regions are then formed. In one embodiment of the invention, a laser doping process is used to form the source-drain extension regions.

摘要翻译： 根据本发明的方法使源极 - 漏极延伸区域暴露的加热步骤的数量最小化，从而使源极 - 漏极延伸区域扩散最小化，并且允许比常规工艺更精确地控制源极 - 漏极扩展区域厚度。 根据本发明，形成邻接栅极的间隔物，然后形成重掺杂的源区和漏区。 栅极和源极和漏极区域被硅化。 随后移除间隔物，然后形成源漏扩展区。 在本发明的一个实施例中，使用激光掺杂工艺来形成源极 - 漏极延伸区域。

公开(公告)号：US06277698B1

公开(公告)日：2001-08-21

申请号：US09382580

申请日：1999-08-25

申请人： Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

发明人： Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/823842

摘要： A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.

摘要翻译： 通过在沉积栅极电极层之前形成电介质膜，半导体器件设置有具有大致矩形轮廓的栅电极。 对电介质膜进行图案化和蚀刻以形成具有由开放区域分开的矩形轮廓的区域。 然后沉积栅极电极层，然后平坦化以形成具有基本上矩形轮廓的栅电极。

公开(公告)号：US06245623B1

公开(公告)日：2001-06-12

申请号：US09187431

申请日：1998-11-06

申请人： Dong-Hyuk Ju ,  Emi Ishida

发明人： Dong-Hyuk Ju ,  Emi Ishida

IPC分类号： H01L218236

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/823814

摘要： A CMOS semiconductor device having shallow source/drain junctions is formed by ion implanting antimony to form lightly doped source/drain regions of an N-channel transistor, thereby reducing channeling for a shallower projected junction depth as compared to conventional N-type impurity implantations. Upon growing a thermal oxide screen layer to protect the substrate from subsequent ion implantations, the implanted antimony experiences oxidation-retarded diffusion, further reducing the projected junction depth. After ion implanting N-type impurities to form moderately or heavily doped source/drain regions and activation annealing, the resulting semiconductor device exhibits the desirably shallow LDD junctions.

摘要翻译： 具有浅源极/漏极结的CMOS半导体器件通过离子注入锑形成，以形成N沟道晶体管的轻掺杂源极/漏极区域，从而与传统的N型杂质注入相比减少了较浅的投影结深度的沟道。 当生长热氧化物屏幕层以保护衬底免于随后的离子注入时，注入的锑经历氧化延迟扩散，进一步降低了投影的结深度。 在离子注入N型杂质以形成适度或重掺杂的源极/漏极区域和激活退火之后，所得的半导体器件表现出期望的浅的LDD结。

公开(公告)号：US06316319B1

公开(公告)日：2001-11-13

申请号：US09357330

申请日：1999-07-20

申请人： Emi Ishida ,  Dong-Hyuk Ju

发明人： Emi Ishida ,  Dong-Hyuk Ju

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/665

摘要： A semiconductor device with shallow junctions is obtained by forming shallow source/drain extensions followed by forming a film over the gate electrode and the semiconductor substrate. The film is formed having a targeted thicknesses to facilitate gate electrode doping and source/drain formation. Ion implantation is then conducted to fully dope the gate electrode and form moderately or heavily doped source/drain implants, thereby reducing gate depletion.

摘要翻译： 通过形成浅的源极/漏极延伸部分，然后在栅电极和半导体衬底上形成膜，获得具有浅结的半导体器件。 形成具有目标厚度的膜以便于栅电极掺杂和源极/漏极形成。 然后进行离子注入以完全掺杂栅电极并形成适度或重掺杂的源极/漏极注入，从而减少栅极耗尽。

公开(公告)号：US06232166B1

公开(公告)日：2001-05-15

申请号：US09187523

申请日：1998-11-06

申请人： Dong-Hyuk Ju ,  Scott Luning

发明人： Dong-Hyuk Ju ,  Scott Luning

IPC分类号： H01L218238

CPC分类号： H01L29/66537 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

摘要： Halo implant regions are formed in a P-channel semiconductor device employing a zero degree tilt angle. N-type impurities are ion implanted to the desired depth in the semiconductor substrate prior to forming P-channel lightly doped source/drain areas. Subsequently, moderately or heavily doped source/drain regions are formed, followed by activation annealing. The halo implants diffuse to form halo structures at the desired location, thereby reducing short channel effects, such as subsurface punchthrough. Other embodiments enable independent control of the junction depths and channel lengths of N- and P-channel transistors, while maintaining high manufacturing throughput.

摘要翻译： 卤素注入区域形成在采用零度倾斜角的P沟道半导体器件中。 在形成P沟道轻掺杂的源极/漏极区之前，将N型杂质离子注入半导体衬底中所需的深度。 随后，形成适度或重掺杂的源极/漏极区，随后进行激活退火。 光晕植入物在期望的位置扩散以形成晕圈结构，从而减少短通道效应，例如地下穿孔。 其他实施例能够独立控制N沟道晶体管和P沟道晶体管的结深度和沟道长度，同时保持高的制造吞吐量。

公开(公告)号：US08536011B2

公开(公告)日：2013-09-17

申请号：US13074836

申请日：2011-03-29

申请人： Shibly S. Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

发明人： Shibly S. Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L29/788

CPC分类号： H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7885 ,  H01L29/792

摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

摘要翻译： 存储器件包括衬底和形成在衬底中的源区和漏区。 源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。 存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

公开(公告)号：US20120228704A1

公开(公告)日：2012-09-13

申请号：US13041512

申请日：2011-03-07

申请人： Dong-Hyuk Ju

发明人： Dong-Hyuk Ju

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/402 ,  H01L29/0878 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66689 ,  H01L29/7816

摘要： A high-voltage transistor is formed in a deep well of a first conductivity type that has been formed in a semiconductor substrate or epitaxial layer of a second conductivity type. A body region of the second conductivity type is formed in the deep well, into which a source region of the first conductivity type is formed. A drain region of the first conductivity type is formed in the deep well and separated from the body region by a drift region in the deep well. A gate dielectric layer is formed over the body region, and a first polysilicon layer formed over the gate dielectric layer embodies the gate of the transistor. The field plate dielectric layer is formed over the drift region after the gate has been formed. Finally, the field plate dielectric is covered by a second polysilicon layer having a field plate positioned over the field plate dielectric layer in the drift region.

摘要翻译： 高压晶体管形成在已经形成在半导体衬底或第二导电类型的外延层中的第一导电类型的深阱中。 第二导电类型的体区形成在深阱中，形成第一导电类型的源极区。 第一导电类型的漏极区域形成在深井中，并且通过深井中的漂移区域与身体区域分离。 栅极电介质层形成在体区上，并且形成在栅极电介质层上的第一多晶硅层体现晶体管的栅极。 在形成栅极之后，在漂移区上形成场板电介质层。 最后，场板电介质被第二多晶硅层覆盖，该第二多晶硅层具有位于漂移区中的场板电介质层上的场板。

公开(公告)号：US06713819B1

公开(公告)日：2004-03-30

申请号：US10118364

申请日：2002-04-08

申请人： William G. En ,  Dong-Hyuk Ju ,  Srinath Krishnan

发明人： William G. En ,  Dong-Hyuk Ju ,  Srinath Krishnan

IPC分类号： H01L2976

CPC分类号： H01L29/78609 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612

摘要： An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

摘要翻译： 一种以绝缘体半导体形式形成的集成电路。 集成电路包括设置在绝缘层上的半导体材料层，其中设置在基板上的绝缘层。 提供第一和第二MOSFET，使得第一MOSFET的源极和漏极中的一个被设置为邻近第二MOSFET的源极和漏极之一。 在半导体材料层中形成非晶区域并从半导体材料层的上表面延伸到隔离层。 非晶区域形成在第一MOSFET的源极和漏极之一的结晶部分和第二MOSFET的源极和漏极之一的结晶部分之间。

公开(公告)号：US06229187B1

公开(公告)日：2001-05-08

申请号：US09420972

申请日：1999-10-20

申请人： Dong-Hyuk Ju

发明人： Dong-Hyuk Ju

IPC分类号： H01L2972

CPC分类号： H01L29/66636 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76264 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/78609

摘要： A silicon on insulator (SOI) wafer is formed with an unoxidized perforation in the insulating silicon dioxide buried oxide layer. A field effect transistor (FET) structure on the SOI wafer is located above the unoxidized perforation such that the unoxidized perforation provides for electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the FET includes masking a silicon wafer prior to an oxygen implantation process to form the unoxidized perforated buried oxide layer in the wafer.

摘要翻译： 绝缘体上硅（SOI）晶片在绝缘二氧化硅掩埋氧化物层中形成有未氧化的穿孔。 SOI晶片上的场效应晶体管（FET）结构位于未氧化穿孔之上，使得未氧化的穿孔提供FET的通道区域与体硅衬底之间的电耦合，以消除由电荷积累引起的浮体效应 由于FET的历史操作导致的通道区域。 形成FET的方法包括在氧注入工艺之前掩蔽硅晶片以在晶片中形成未氧化的穿孔掩埋氧化物层。